MAX1415 Datasheet, PDF (4/36 Pages) Maxim Integrated Products – 16-Bit, Low-Power, 2-Channel, Sigma-Delta ADCs

16-Bit, Low-Power, 2-Channel,
Sigma-Delta ADCs
ELECTRICAL CHARACTERISTICS—MAX1415 (continued)
(V_DD = 3V, GND = 0, V_REF+ = 1.225V, V_REF- = GND, external f_CLKIN = 2.4576MHz, CLKDIV bit = 0, C_REF+ to GND = 0.1µF, C_REF- to
GND = 0.1µF, T_A = T_MIN to T_MAX, unless otherwise noted.)
PARAMETER
Output-Voltage High
Tri-State Leakage Current
Tri-State Output Capacitance
SYSTEM CALIBRATION
Full-Scale Calibration Range
SYMBOL
CONDITIONS
V_OH
DOUT and DRDY, I_SOURCE = 100µA
CLKOUT, I_SOURCE = 10µA
I_L
C_OUT
DOUT only
DOUT only
GAIN = selected PGA gain (1 to 128)
(Note 10)
MIN
V_DD -
0.6V
V_DD -
0.6V
TYP
9
MAX UNITS
V
±10
µA
pF
-1.05 ×
V_REF /
GAIN
1.05 ×
V_REF /
V
GAIN
Offset Calibration Range
GAIN = selected PGA gain (1 to 128)
(Note 10)
-1.05 ×
V_REF /
GAIN
1.05 ×
V_REF /
V
GAIN
Input Span
GAIN = selected PGA gain (1 to 128)
(Notes 10, 11)
0.8 ×
V_REF /
GAIN
2.1 ×
V_REF /
V
GAIN
POWER REQUIREMENTS
Power-Supply Voltage
V_DD
2.7
Unbuffered, f_CLKIN = 1MHz, gain = 1 to 128
Buffered, f_CLKIN = 1MHz, gain = 1 to 128
3.6
V
0.40
0.725
Power-Supply Current (Note 12)
Unbuffered,
Gain = 1 to 4
I_DD
f_CLKIN = 2.4576MHz
Gain = 8 to 128
0.55
mA
0.55
Buffered,
f_CLKIN = 2.4576MHz
Gain = 1 to 4
Gain = 8 to 128
0.825
1.0
Power-down mode (Note 13)
8
µA
Power-Supply Rejection Ratio
PSRR V_DD = 2.7V to 3.6V
(Note 14)
dB
EXTERNAL-CLOCK TIMING SPECIFICATIONS
CLKIN Frequency
f_CLKIN (Note 15)
400
2500 kHz
Duty Cycle
40
60
%
INTERNAL-CLOCK TIMING SPECIFICATIONS
MAX1415AE__,
f_CLK = 1MHz (CLK = 0)
or 2.4576MHz (CLK = 1)
T_A = -40°C to
+85°C
±4
Internal-Clock Frequency
f_CLK
MAX1415C__,
f_CLK = 1MHz (CLK = 0)
or 2.4576MHz (CLK = 1)
T_A = 0°C to
+70°C
±4
%
MAX1415E__,
T_A = -40°C to 0°C
±7
f_CLK = 1MHz (CLK = 0)
or 2.4576MHz (CLK = 1) TA= 0°C to +85°C
±4
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