MAX1415 Datasheet, PDF (31/36 Pages) Maxim Integrated Products – 16-Bit, Low-Power, 2-Channel, Sigma-Delta ADCs

16-Bit, Low-Power, 2-Channel,
Sigma-Delta ADCs
Next, an internally generated voltage (V_REF/GAIN) is
applied across AIN+ and AIN-. This condition results in
the full-scale calibration.
Start self-calibration by setting MD1 = 0, MD0 = 1, and
FSYNC = 0 in the setup register. Self-calibration com-
pletes in 6 x 1/output data rate. The MD1 and MD0 bits
both return to 0 at the end of calibration. The device
returns to normal acquisition mode and performs a con-
version, which completes in 3 x 1/output data rate after
the self-calibration sequence.
The DRDY output goes high at the start of calibration
and falls low when the calibration is complete and the
next conversion result is valid in the data register. The
total time for self-calibration and one conversion (time
until DRDY goes low) is 9 x 1/output data rate. If DRDY
is low before or goes low during the calibration com-
mand write to the setup register, DRDY takes up to one
additional modulator cycle (128/f_CLKIN) to return high to
indicate a calibration or conversion in progress.
System Calibration
System calibration compensates for offset and gain
errors for the entire analog signal path including the
ADC, signal conditioning, and signal source. System
calibration is a two-step process and requires individ-
ual zero-scale and full-scale calibrations on the select-
ed channel at a specified PGA gain. Recalibration is
recommended with changes in ambient temperature,
supply voltage, buffered/unbuffered mode, bipolar/
unipolar mode, PGA gain, and output data rate.
Set the zero-scale reference point across AIN+ and AIN-.
Start the zero-scale calibration by setting MD1 = 1, MD0
= 0, and FSYNC = 0 in the setup register. When zero-
scale calibration is complete (3 x 1/output data rate),
MD1 and MD0 both return to 0. DRDY goes high at the
start of the zero-scale system calibration and returns low
when there is a valid word in the data register (4 x 1/out-
put data rate). The time until DRDY goes low is com-
prised of one zero-scale calibration sequence (3 x
1/output data rate) and one conversion on the AIN volt-
age (1 x 1/output data rate). If DRDY is low before or
goes low during the calibration command write to the
setup register, DRDY takes up to one additional modula-
tor cycle (128/f_CLKIN) to return high to indicate a calibra-
tion or conversion in progress.
After performing a zero-scale calibration, connect the
analog inputs to the full-scale voltage level
(V_REF/GAIN). Perform a full-scale calibration by setting
MD1 = 1 and MD0 = 1. After 3 x 1/output data rate,
MD1 and MD0 both return to 0 at the completion of full-
scale calibration. DRDY goes high at the beginning of
calibration and returns low after calibration is complete
and new data is in the data register (4 x 1/output data
rate). The time until DRDY goes low is comprised of
one full-scale calibration sequence (3 x 1/output data
rate) and one conversion on the AIN voltage (1 x 1/out-
put data rate). If DRDY is low before or goes low during
the calibration command write to the setup register,
DRDY takes up to one additional modulator cycle
(128/f_CLKIN) to return high to indicate a calibration or
conversion in progress.
In bipolar mode, the midpoint (zero scale) and positive
full scale of the transfer function are used to calculate the
calibration coefficients of the gain and offset registers. In
unipolar mode, system calibration is performed using the
two endpoints of the transfer function (Figures 4 and 5).
Power-Down Modes
The MAX1415/MAX1416 include a power-down mode to
save power. Select power-down mode by setting PD = 1
in the communications register. The PD bit does not
affect the serial interface or the status of the DRDY line.
While in power-down mode, the MAX1415/MAX1416
retain the contents of all of its registers. Placing the part
in power-down mode reduces current consumption to
2µA (typ) when in external CMOS clock mode and with
CLKIN connected to V_DD or GND. If DRDY is high before
the part enters power-down mode, then DRDY remains
high until the part returns to normal operation mode and
new data is available in the data register. If DRDY is low
before the part enters power-down mode, indicating new
data in the data register, the data register can be read
during power-down mode. DRDY goes high at the end of
this read operation. If the new data remains unread,
DRDY stays low until the MAX1415/MAX1416 are taken
out of power-down mode and resume data conversion.
Resume normal operation by setting PD = 0. The device
begins a new conversion with a result appearing in 3 x
1/output data rate + t_P, where t_P = 2000 x 1/f_CLKIN, after
PD is set to 0. If the clock is stopped during power-down
mode, allow sufficient time for the clock to startup before
resuming conversion.
If the external crystal/resonator is used and CLKDIS =
0, CLKOUT remains active during power-down mode to
provide a clock source for other devices in the system.
If the internal oscillator is used, power-down mode
shuts off the internal oscillator.
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