MAX1415 Datasheet, PDF (29/36 Pages) Maxim Integrated Products – 16-Bit, Low-Power, 2-Channel, Sigma-Delta ADCs

16-Bit, Low-Power, 2-Channel,
Sigma-Delta ADCs
POWER-ON RESET
INITIALIZE µC/µP SERIAL
PORT
WRITE TO THE COMMUNICATIONS
REGISTER. SELECT CHANNEL 1 AND SET
NEXT OPERATION AS A WRITE TO THE
CLOCK REGISTER
(0x20)
WRITE TO THE CLOCK REGISTER. ENABLE
INTERNAL CLOCK. SET CLOCK FREQUENCY
TO 2.4576MHz. SELECT OUTPUT UPDATE
RATE OF 60Hz.
(0xA5)
WRITE TO THE COMMUNICATIONS
REGISTER. SET NEXT OPERATION AS
A WRITE TO THE SETUP REGISTER.
(0x10)
WRITE TO THE SETUP REGISTER. SET
SELF-CALIBRATION MODE, GAIN TO 0,
UNIPOLAR MODE, UNBUFFERED MODE.
BEGIN SELF-CALIBRATION/CONVERSION
BY CLEARING FSYNC.
(0x44)
HARDWARE POLLING
SOFTWARE POLLING
1 (DATA
NOT
READY)
POLL DRDY
OUTPUT
WRITE TO COMMUNICATIONS REGISTER.
SET NEXT OPERATION AS A READ FROM
THE COMMUNICATIONS REGISTER.
(0x08)
READ THE COMMUNICATIONS REGISTER
(8 BITS)
0 (DATA
READY)
WRITE TO THE COMMUNICATIONS
REGISTER. SET NEXT OPERATION AS A
READ FROM THE DATA REGISTER.
(0x38)
POLL DRDY
BIT
1 (DATA NOT
READY)
0 (DATA
READY)
READ THE DATA REGISTER
(16 BITS)
Figure 11. Sample Flow Diagram for Data Conversion
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