MAX1415 Datasheet, PDF (25/36 Pages) Maxim Integrated Products – 16-Bit, Low-Power, 2-Channel, Sigma-Delta ADCs

16-Bit, Low-Power, 2-Channel,
Sigma-Delta ADCs
Table 6. Communications Register
(MSB)
FUNCTION
Name
Defaults
COMMUNICATION
START/DATA READY
0/DRDY
0
REGISTER SELECT
RS2 RS1 RS0
0
0
0
Table 7. Register Selection
RS2
RS1
RS0
REGISTER
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Communications register
Setup register
Clock register
Data register
Test register*
No operation
Offset register
Gain register
*The test register is used for factory testing only.
Table 8. Channel Selection
READ/WRITE
SELECT
R/W
0
POWER-DOWN
MODE
PD
0
(LSB)
CHANNEL SELECT
CH1
0
CH0
0
POWER-ON RESET STATUS
0x00
0x01
0x85
N/A
N/A
—
0x1F 40 00
0x57 61 AB
REGISTER SIZE
(bits)
8
8
8
16
8
—
24
24
CH1
0
0
1
1
CH0
0
1
0
1
AIN+
AIN1+
AIN2+
AIN1-
AIN1-
AIN-
AIN1-
AIN2-
AIN1-
AIN2-
OFFSET/GAIN
REGISTER PAIR
0
1
0
2
Table 9. Setup Register
(MSB)
FUNCTION MODE CONTROL
Name
Defaults
MD1
0
MD0
0
PGA GAIN CONTROL
G2
G1
G0
0
0
0
BIPOLAR/UNIPOLAR
MODE
B/U
0
BUFFER ENABLE
BUF
0
(LSB)
FSYNC
FSYNC
1
G2, G1, G0: (Default = 0, 0, 0) Gain-Selection Bits. See
Table 11 for PGA gain settings.
B/U: (Default = 0) Bipolar-/Unipolar-Mode Selection:
Set B/U = 0 to select bipolar mode. Set B/U = 1 to
select unipolar mode.
BUF: (Default = 0) Buffer-Enable Bit. For unbuffered
mode, disable the internal buffer of the MAX1415/
MAX1416 to reduce power consumption by writing a 0 to
the BUF bit. Write a 1 to this bit to enable the buffer. Use
the internal buffer when acquiring high source-imped-
ance input signals.
FSYNC: (Default = 1) Filter-Synchronization/
Conversion-Start Bit. Set FSYNC = 0 to begin calibration
or conversion. The MAX1415/MAX1416 perform free-run-
ning conversions while FSYNC = 0. Set FSYNC = 1 to
stop converting data and to hold the nodes of the digital
filter, the filter-control logic, the calibration-control logic,
and the analog modulator in a reset state. The DRDY
output does not reset high if it is low (indicating that valid
data has not yet been read from the data register) when
FSYNC goes high. To clear DRDY output, read the data
register.
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