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MAX1415 Datasheet, PDF (7/36 Pages) Maxim Integrated Products – 16-Bit, Low-Power, 2-Channel, Sigma-Delta ADCs
16-Bit, Low-Power, 2-Channel,
Sigma-Delta ADCs
ELECTRICAL CHARACTERISTICS—MAX1416 (continued)
(VDD = 5V, GND = 0, VREF+ = 2.5V, VREF- = GND, fCLKIN = 2.4576MHz, CLKDIV bit = 0, CREF+ to GND = 0.1µF, CREF- to GND =
0.1µF, TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER
SYMBOL
EXTERNAL REFERENCE (REF+, REF-)
REF Differential Input Range
REF Absolute Input Voltage
VREF
REF Input Capacitance
CONDITIONS
(Note 9)
Gain = 1 to 128
REF Input Sampling Rate
fs
DIGITAL INPUTS (DIN, SCLK, CS, RESET)
Input High Voltage
Input Low Voltage
Input Hysteresis
VIH
VIL
VHYST
DIN, CS, RESET
SCLK
Input Current
IIN
Input Capacitance
CLKIN INPUT
CLKIN Input High Voltage
CLKIN Input Low Voltage
VCLKINH
VCLKINL
CLKIN Input Current
ICLKIN
DIGITAL OUTPUTS (DOUT, DRDY, CLKOUT)
Output-Voltage Low
VOL
Output-Voltage High
VOH
Tri-State Leakage Current
IL
DOUT and DRDY, ISINK = 800µA
CLKOUT, ISINK = 10µA
DOUT and DRDY, ISOURCE = 200µA
CLKOUT, ISOURCE = 10µA
DOUT only
Tri-State Output Capacitance
COUT DOUT only
SYSTEM CALIBRATION
MIN TYP MAX UNITS
1
GND
3.5
V
VDD
V
10
pF
fCLKIN / MHz
64
2
V
0.8
V
250
mV
500
±1
µA
5
pF
3.5
V
0.8
V
±10
µA
0.4
V
0.4
4.0
V
4.0
±10
µA
9
pF
Full-Scale Calibration Range
GAIN = selected PGA gain (1 to 128)
(Note 10)
-1.05 ×
VREF /
GAIN
+1.05 ×
VREF /
V
GAIN
Offset Calibration Range
GAIN = selected PGA gain (1 to 128)
(Note 10)
-1.05 ×
VREF /
GAIN
+1.05 ×
VREF /
V
GAIN
Input Span
POWER REQUIREMENTS
Power-Supply Voltage
GAIN = selected PGA gain (1 to 128)
(Notes 10, 11)
VDD
0.8 ×
VREF /
GAIN
4.75
2.1 ×
VREF /
V
GAIN
5.25
V
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