MAX1415 Datasheet, PDF (24/36 Pages) Maxim Integrated Products – 16-Bit, Low-Power, 2-Channel, Sigma-Delta ADCs

16-Bit, Low-Power, 2-Channel,
Sigma-Delta ADCs
DIN
DOUT
RS2 RS1 RS0
COMMUNICATIONS REGISTER
SETUP REGISTER (8 BITS)
CLOCK REGISTER (8 BITS)
DATA REGISTER (16 BITS)
TEST REGISTER (8 BITS)*
OFFSET REGISTER (24 BITS)
GAIN REGISTER (24 BITS)
REGISTER
SELECT
DECODER
*THE TEST REGISTER IS USED FOR FACTORY TESTING ONLY.
Figure 10. Register Summary
The default state of the MAX1415/MAX1416 is to wait
for a write to the communications register. Any write or
read operation on the MAX1415/MAX1416 is a two-step
process. First, a command byte is written to the com-
munications register. This command selects the input
channel, the desired register for the next read or write
operation, and whether the next operation is a read or a
write. The second step is to read from or write to the
selected register. At the end of the data-transfer cycle,
the device returns to the default state. See the
Performing a Conversion section for examples.
If the serial communication is lost, write 32 ones to the ser-
ial interface to return the MAX1415/MAX1416 to the default
state. The registers are not reset after this operation.
Communications Register
The byte-wide communications register is bidirectional
so it can be written and read. The byte written to the
communications register indicates the next read or write
operation on the selected register, the power-down
mode, and the analog input channel (see Table 6). The
DRDY bit indicates the conversion status.
0/DRDY: (Default = 0) Communication-Start/Data-Ready
Bit. Write a 0 to the 0/DRDY bit to start a write operation to
the communications register. If 0/DRDY = 1, then the
device waits until a 0 is written to 0/DRDY before continu-
ing to load the remaining bits. For a read operation, the
0/DRDY bit shows the status of the conversion. The
DRDY bit returns a 0 if the conversion is complete and
the data is ready. DRDY returns a 1 if the new data has
been read and the next conversion is not yet complete. It
has the same value as the DRDY output pin.
RS2, RS1, RS0: (Default = 0, 0, 0) Register-Select Bits.
RS2, RS1, and RS0 select the next register to be
accessed as shown in Table 7.
R/W: (Default = 0) Read-/Write-Select Bit. Use this bit to
select if the next register access is a read or a write
operation. Set R/W = 0 to select a write operation, or set
R/W = 1 for a read operation on the selected register.
PD: (Default = 0) Power-Down Control Bit. Set PD = 1
to initiate power-down mode. Set PD = 0 to take the
device out of power-down mode. If the internal oscilla-
tor or external crystal/resonator is used and CLKDIS =
0, CLKOUT remains active during power-down mode to
provide a clock source for other devices in the system.
CH1, CH0: (Default = 0, 0) Channel-Select Bit. Write to
the CH1 and CH0 bits to select the conversion channel or
to access the calibration data shown in Table 8. The cali-
bration coefficients of a particular channel are stored in
one of the three offset and gain register pairs in Table 8.
Set CH1 = 1 and CH0 = 0 to evaluate the noise perfor-
mance of the part without external noise sources. In this
noise-evaluation mode, connect AIN1- to an external volt-
age within the allowable common-mode range.
Setup Register
The byte-wide setup register is bidirectional so it can
be written and read. The byte written to the setup regis-
ter sets the calibration modes, PGA gain, unipolar/bipo-
lar mode, buffer enable, and conversion start (see
Table 9).
MD1, MD0: (Default = 0, 0) Mode-Select Bits. See
Table 10 for normal operating mode, self-calibration,
zero-scale calibration, or full-scale calibration-mode
selection.
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