MAX14001 Datasheet, PDF (5/34 Pages) Maxim Integrated Products – Configurable, Isolated 10-bit ADCs for Multi-Range Binary Inputs

MAX14001/MAX14002
Configurable, Isolated 10-bit ADCs for
Multi-Range Binary Inputs
Electrical Characteristics (continued)
(V_DDL - V_GNDL = 1.71V to 5.5V, V_DD - V_GNDL = 3.0V to 3.6V, R_ISET = 120kΩ, T_A = -40°C to +125°C, V_GNDF = V_GNDL. Typical values
are at T_A = +25°C with V_DDL = V_DD = +3.3V, R_ISET = 120kΩ, V_GNDF = V_GNDL.) (Notes 2, 3)
PARAMETER
SYMBOL
Output High Voltage
Output Low Voltage
Output High-Impedance
Leakage Current
V_OH
V_OL
I_OL
Input Leakage Current
I_IL
Input Capacitance
C_IN
SPI TIMING CHARACTERISTICS
SCLK Clock Frequency
SCLK Clock Period
SCLK Pulse-Width High
SCLK Pulse-Width Low
CS Fall-to-SCLK Rise
Time
f_SCLK
t_SCLK
t_SCLKH
t_SCLKL
t_CS(lead)
CONDITIONS
SDO, COUT, sourcing 4mA
SDO, COUT, FAULT, sinking 4mA
SDO, FAULT
SCLK, SDI, CS
SCLK, SDI, CS, f = 1MHz
Single device
Single device
Single device
Single device
MIN
TYP
V_DDL- 0.4
-1
-1
2
MAX
0.4
+1
+1
UNITS
V
V
µA
µA
pF
5
MHz
200
ns
80
ns
80
ns
80
ns
SCLK Fall-to-CS Rise
Time
t_CS(lag)
80
SDI Hold Time
t_DINH
40
SDI Setup Time
t_DINSU
40
SDO Enable Time (CS
Falling to SDO Valid)
t_DOUT(en) C_L = 50pF
40
SDO Disable Time (CS
Rising to SDO Three-
t_DOUT(dis) C_L = 50pF
40
State)
Output Data Propagation
Delay
t_DO
C_L = 50pF. SCLK falling-edge to SDO valid
Write-Command to Field
Implementation Delay
t_FID
From CS de-assertion until field-side registers
are loaded
Inter-Access Gap
t_IAG
Minimum time CS must be de-asserted between
commands
920
ns
ns
ns
ns
ns
50
ns
165
ns
ns
Note 2: All devices are 100% production tested at T_A = +25°C. Specifications for all temperature limits are guaranteed by design.
Note 3: All currents into the device are positive; all currents out of the device are negative. All voltages are referenced to their
respective ground (GNDL or GNDF), unless otherwise noted.
Note 4: Guaranteed by characterization; not production tested.
Note 5: EFT voltage according to IEC 61004-4 is tested through direct coupling to the generator.
Note 6: CMTI is the maximum sustainable common-mode voltage slew rate while maintaining the correct output states. CMTI
applies to both rising and falling common-mode voltage edges. Tested with the transient generator connected between
GNDF and GNDL (V_CM = 1000V).
Note 7: Latency numbers are based on the following condition: a full-scale step is applied at the ADC input and THU is set to mid-scale
value (0x1ff). Latency is the delay from the step at the ADC input to the digital comparator output.
www.maximintegrated.com
Maxim Integrated │  5