MAX14001 Datasheet, PDF (27/34 Pages) Maxim Integrated Products – Configurable, Isolated 10-bit ADCs for Multi-Range Binary Inputs

MAX14001/MAX14002
Configurable, Isolated 10-bit ADCs for
Multi-Range Binary Inputs
ENBL (Read/Write)
Address = 0x0A
Default = 0x000
The ENA bit in the ENBL register enables the inrush and bias current. At POR, ENA is set to “0”. After programming
all the configuration registers, the user sets ENA to “1”, which enables the IFET current sink. This procedure prevents
unintentional currents from flowing during the configuration process. It is recommended to set this bit at the very end of
the configuration procedure.
BIT
FIELD NAME
DESCRIPTION
3:0
ENBL[3:0]
Unused
4
ENA
0: Prevents the field-side current sink (default)
1: Enables the field-side current sink
9:5
ENBL[9:5]
Unused
ACT (Write and Clear)
Address = 0x0B
Default = 0x000
Immediate action register. When a bit is written to this register, action is taken immediately and the bit is then cleared.
Note: The SRES bit (bit 6) resets only the SPI registers while the RSET bit (bit 7) is acting as the global POR, the DC-DC
converter will turn off and field-side will be reset as well as the logic-side (SPI interface).
BIT
FIELD NAME
DESCRIPTION
5:0
ACT[5:0]
Unused
Software reset. Restores all registers to their POR value.
6
SRES
0: Normal operation (default)
1: Software reset
Reset. Has the same effect as a power on reset.
7
RSET
0: Normal operation (default)
1: Reset
8
ACT8
Unused
Trigger an inrush current pulse. Has no effect when ENA = 0 (in the ENBL Register)
9
INPLS
0: Normal operation (default)
1: Trigger an inrush current
WEN (Read/Write)
Address = 0x0C
Default = 0x000
Write enable register. A value of 0x294 in this register enables writing to the SPI registers. Set to 0x294 prior to writing
to any configuration or verification registers. Set to 0x000 after configuring all registers. Its purpose is to make it highly
unlikely that any settings will be unintentionally changed by noise on the SPI bus.
Note: This register should be reset to 0x000 after configuring the device prior to normal operation.
BIT
FIELD NAME
DESCRIPTION
9:0
WEN[9:0]
This register must be set to 0x294 prior to writing to any SPI registers.
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