MAX14001 Datasheet, PDF (15/34 Pages) Maxim Integrated Products – Configurable, Isolated 10-bit ADCs for Multi-Range Binary Inputs

MAX14001/MAX14002
Configurable, Isolated 10-bit ADCs for
Multi-Range Binary Inputs
FAST Mode
1) The high-voltage FET is trying to sink the inrush
current, but cannot because the input signal is not
supplying enough current. Since the current level
cannot be met, the FET current is set to the inrush
level, and the inrush timer is reset.
2) The input voltage increases and supplies enough current
for the inrush pulse. The inrush timer is started.
3) The inrush timer expires and the FET current is
reduced to the bias level.
4) The input voltage drops and can no longer supply the
bias current. The inrush timer is reset and the FET
current is set to the inrush level.
5) Contact bounce raises the input voltage and supplies
enough current for an inrush pulse. The inrush timer
is started.
6) The input voltage drops and can no longer supply the
inrush current. The inrush timer is reset and the FET
current remains the inrush level.
7) The noise pulse is fully clamped at the turn-on voltage
of the FET circuit.
8) Higher energy noise pulse is fully clamped by the inrush
current. Noise current exceeds the bias current, but
since the FET is trying to sink the larger input current,
the input current rises and the voltage remains clamped
at the turn-on voltage of the FET circuit.
Repetitive Inrush Pulse Limiting (MAX14001 Only)
The MAX14001 can limit repetitive inrush pulses to
prevent overheating from abnormal input signals that
would otherwise trigger a continuous stream of inrush
pulses. When the pulse limiting function is enabled, the
MAX14001 monitors the percentage of time that the
inrush current is flowing. When it exceeds the duty cycle
threshold over the last 10 seconds, additional inrush
pulses are disabled for the next 10 seconds. When the
pulse limiting is triggered, the INRD bit in the FLAGS
register is set and FAULT is asserted if the EINRD bit in
the FLTEN register is set. The pulse limiting function can
be turned off or the pulse duty cycle can be set to 1.6%,
3.1%, or 6.3% using the DU[1:0] bits in the INRP register.
The MAX14002 does not provide a repetitive inrush pulse
limiting feature.
Diagnostic and Fault Reporting Features
The MAX14001/MAX14002 continuously monitor seven
possible fault conditions, and a hardware alert is provided
via the open drain FAULT pin, which asserts low when an
enabled fault is detected. The possible faults are: ADC
functionality error, repetitive inrush pulses being triggered,
SPI framing error, loss of internal isolated data stream,
CRC errors from internal communication, high-voltage
FET failure, and corrupted memory error.
The bits in the FLTEN register determine how the FAULT
output responds to the seven error conditions, and the
FAULT output is asserted if the corresponding bit is
enabled in the FLTEN register. If the FLTEN register bit
DYEN = 0, FAULT operates as a latched output and remains
asserted until the FLAGS register is cleared but if the bit
DYEN = 1, FAULT operates as a dynamic output and
de-asserts when the faults are no longer detected even
though bits in the FLAGS register remain set.
If the corresponding bit in the FLTEN register is not set,
when an error is flagged, FAULT will not be asserted,
but the bit in the FLAGS register will still be latched and
remain set until the register is read, which automatically
clears all bits in the FLAGS register. Note that if a fault
condition still exists when the register is read, the cleared
fault bit will immediately be set again.
In a typical application, FAULT triggers an interrupt routine
in the microcontroller or FPGA, which will read the FLAGS
register to determine the cause of the interrupt.
Diagnostic Conditions
The diagnostic features implemented on the MAX14001/
MAX14002 can be summarized as follows:
1) ADC Functionality Error: ADC functionality is
checked by looking for changes in the ADC output. To
ensure that a change should have occurred, a special
test measurement is made while injecting a small cur-
rent at the input of the ADC. This special measurement
used for ADC functionality verification is interleaved
between normal measurements and does not affect
the ADC sampling time. If the ADC reading does not
change, an ADC functional failure is declared and bit
ADC (bit 1) in the FLAGS register is set.
2) Repetitive Inrush Pulses: If the repetitive inrush pulse
limiting feature of the MAX14001 is turned on, and
pulse limiting is triggered, bit INRD (bit 2) in the FLAGS
register is set. See Repetitive Inrush Pulse Limiting
(MAX14001 Only) for details on inrush pulse limiting.
3) SPI Framing Error: After CS transitions from low to
high, if the number of bits clocked in while CS was
low is not an integer multiple of 16, an SPI framing
error is declared and bit SPI (bit 3) in the FLAGS
register is set. The instruction in the SPI shift register
is not decoded and no register value is changed.
4) Loss of Data Stream: The field-side sends ADC
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