MAX14001 Datasheet, PDF (16/34 Pages) Maxim Integrated Products – Configurable, Isolated 10-bit ADCs for Multi-Range Binary Inputs

MAX14001/MAX14002
Configurable, Isolated 10-bit ADCs for
Multi-Range Binary Inputs
data across the isolation barrier to the logic-side
every 100µs, except for the startup period. If the
periodic field-side data is not received, a loss of
data stream fault is declared and bit COM (bit 4) in
the FLAGS register is set. It is possible to recover
from a loss of data stream fault by asserting a hard
reset through the ACT register, which will return all
of the registers to their default state, thus requiring
the MAX14001/MAX14002 to go through the startup
configuration process.
5) CRC Errors From Internal Communication: Internal
communication across the isolation barrier includes
a CRC code to ensure that corrupt data does not
cause system problems. If the CRC indicates an error,
the received data is discarded. If six consecutive
CRCs fail, a CRC fault is declared and bit CRCL (bit
5) or CRCF (bit 6) in the FLAGS register is set.
6) High-Voltage FET Failure: If the ADC reading is greater
than the inrush re-arm threshold (INRR), and IFET is
not able to sink the programmed current, a FET fault
is declared and bit FET (bit 7) in the FLAGS register is
set. INRR is permanently set to 0x0C0 in MAX14002.
7) Memory Error: The devices continually compare the
bits of each verification register to the bits of their
corresponding configuration register. If any of the bits
do not match, a memory fault is declared and bit MV
(bit 8) in the FLAGS register is set. No information on
which register failed is provided. Note that the default
value for each verification register is the complement of
its corresponding configuration register, which guarantees
an MV fault any time power is lost and restored.
FAULT at Power-On
The devices’ internal memory is volatile and must be
reprogrammed after power cycling. To protect against
undetected power glitches and the remote possibility that
a memory bit would be lost during years of static
operation, the devices monitor their configuration
registers and assert bit MV (bit 8) in the FLAGS
register any time the memory is corrupted. Verification
registers have complementary POR values compared to
the configuration registers, and therefore the MAX14001/
MAX14002 start with a memory fault condition and assert
the FAULT pin at startup.
Isolated Power and Data Transfer
A simplified view of the isolated power and data transfer
sections is shown in the Functional Diagram. The logic-side
supply V_DD powers an integrated, inductively coupled,
DC-DC converter that generates a nominal 3V with just
enough output current to power the field-side of the
MAX14001/MAX14002 and an external 70µA voltage
reference. No other circuits should be powered from the
field-side of the MAX14001/MAX14002.
Serial data is transferred by capacitively-isolated differential
transceivers. To verify reliable communication through the
isolation barrier, a cyclic redundancy check (8-bit CRC)
is embedded in the transmitted serial data streams. If a
CRC fails, the data is discarded and no action is taken. If
six consecutive CRCs fail, the CRC bit in the FLAGS register
is set and FAULT is asserted if the CRC fault enable bit is
set in the FLTEN register.
Configuration and Monitoring
An SPI interface is used for transferring configuration,
control and diagnostic data as well as ADC readings
between a master (FPGA or microcontroller) and single/
multiple MAX14001/MAX14002(s). The interface can
support daisy-chain configuration and consists of four
ports: SCLK, CS, SDI and SDO.
SPI Interface
SPI communication includes the following features:
●● Support for daisy-chain operation
●● Able to verify the previous command was correctly
received by reading SDO on the next instruction cycle
●● Able to read/verify all written registers (except ACT
register)
●● Identify when commands are not a multiple of 16-bits
and set the SPI fault flag
●● Commands of all 0s or all 1s do not change any
writable registers
●● A single command cannot program both the
configuration and verification register
●● Serial clock up to 5MHz
The command is 16-bits in length and the structure of the
16-bit data is shown in the Table 2.
Table 2. SPI Command
ADDRESS
5-bits A[4:0], MSB to LSB
CONTROL
W/R bit, Read = 0, Write = 1
DATA
10-bits D[9:0], MSB to LSB
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