MAX14001 Datasheet, PDF (31/34 Pages) Maxim Integrated Products – Configurable, Isolated 10-bit ADCs for Multi-Range Binary Inputs

MAX14001/MAX14002
Configurable, Isolated 10-bit ADCs for
Multi-Range Binary Inputs
MAX14002 vs. MAX14001
The MAX14002 is a reduced functionality version of the
MAX14001. The MAX14002 only works in FAST mode
and does not limit the number of inrush pulses. In the
MAX14002, write access is permanently disabled to three
registers: INRR, INRT, and INRP. In addition to disabling
write access to these registers, the three corresponding
verification registers INRRV, INRTV, and INRPV will
default to the same value as the configuration registers,
and an MV fault in the FLAGS register related to these
registers is not generated during startup unless the
memory is corrupted.
All other functions are the same as the MAX14001.
Applications Information
Typical Application Circuit
The MAX14001/MAX14002 are designed for industrial
configurable binary input applications. The input voltage
on the field-side is continuously measured by the integrated
ADC, and results are transmitted across the isolation
barrier and compared to the programmable high and low
thresholds on the logic-side. The COUT pin presents the
real-time result of the comparison and notifies the system
if the binary input is a logic-high/logic-low voltage level.
The MAX14001/MAX14002 also provide current control
through a high-voltage depletion mode FET. While the
drain of the high-voltage FET is connected to the binary
module input, the gate voltage of the FET is set at a
nominal 3.6V by the MAX14001/MAX14002’s GATE pin.
The IFET pin is connected to the source of the FET to sink
a programmable inrush or bias current. When the binary
module input voltage is higher than the trigger threshold,
typically in the case of an external relay closing, an inrush
current is triggered to clean the relay contacts. Control
of the inrush current allows the binary input module to
be used in different pulse counting and relay monitoring
applications. See the Typical Application Circuit for
connection between the devices and the high-voltage FET.
These devices are configured and monitored through an
SPI interface. The FAULT output can be configured to
generate an interrupt when certain errors are detected
by the embedded self-diagnostic circuit. FAULT is an
open-drain digital output so an external pullup resistor is
needed, typically 4.7kΩ.
Layout, Grounding and Bypassing
Power Supply Recommendations
It is recommended to decouple both the V_DD and V_DDL
supplies with 10µF capacitors in parallel with 1000pF
capacitors to GNDL. Place the 1000pF capacitors as close
to V_DD and V_DDL as possible. It is preferred to decouple
the V_DD pin through the GNDL pin 11, and the V_DDL pin
through the GNDL pin 19. The V_DDF pin is the integrated
DC-DC converter output and it is recommended to decou-
ple it with low-ESR capacitors of 0.1µF in parallel with
1000pF to GNDF (pin 10). Place the 1000pF capacitor as
close to V_DDF as possible.
For best performance, bypass the GATE pin to the GNDF
plane with a low-ESR capacitor of 0.01µF and bypass the
IFET pin to the GNDF plane with a low-ESR capacitor of
1000pF. REFIN is the optional external voltage reference
input, and, for best performance, bypass REFIN to AGND
with a 0.1µF ceramic capacitor when an external voltage
reference is used. Refer to the Typical Application Circuit
for a connection example.
Layout Considerations
It is recommended to design an isolation or keep-out
channel underneath the MAX14001/MAX14002 that is
free from ground and signal planes. Any galvanic or
metallic connection between the field-side and the logic-
side defeats the isolation.
Ensure that the decoupling capacitors between V_DDL,
V_DD and GNDL and between V_DDF and GNDF are located
as close as possible to the IC to minimize inductance.
Route important signal lines close to the ground plane to
minimize possible external influences. On the field-side,
it is good practice to separate the ADC input and voltage
reference ground AGND from the GATE and IFET reference
ground GNDF.
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