MAX14001 Datasheet, PDF (13/34 Pages) Maxim Integrated Products – Configurable, Isolated 10-bit ADCs for Multi-Range Binary Inputs

MAX14001/MAX14002
Configurable, Isolated 10-bit ADCs for
Multi-Range Binary Inputs
Table 1. Voltage Reference Register Configuration
REFERENCE
CONFIGURATION
Internal Reference
External Series Reference
External Shunt Reference
CFG:EXRF
0
1
1
CFG:EXTI
0
0
1
CONNECTION
Connect REFIN directly to AGND.
Series reference is supplied by V_DDF. Output is connected to the REFIN
pin. Bypass REFIN to AGND with a 0.1μF capacitor.
Internal current source is turned on. Shunt reference is connected between
REFIN and AGND. Bypass REFIN to AGND with a 0.1μF capacitor.
ADC Error
The uncalibrated error of the ADC lies within the window
shown in the Figure 3 ADC Error Window. The boundaries
of the box are defined by the offset and gain error from
the EC table and include INL errors as well as drift over
temperature. The upper-boundary is set by the most
positive offset combined with the most positive gain error.
Conversely, the lower-boundary is set by the most negative
offset combined with the most negative gain error.
ERROR_MAX = OE × FS + V_IN x GE
Where OE is the offset error in %FS, FS is the full scale
voltage, V_IN is the input voltage being measured, and GE
is the gain error in %.
If a resistor-divider is used in front of the ADC, FS and
V_IN can be the voltages at the input of the divider. For
total system error, the resistive-divider error and the error
of the voltage reference in percent are added to the gain
error of the ADC.
SYSTEM ERROR_MAX = OE × FS + V_IN x
(GE + ERROR_R + ERROR_VREF)
Where OE is the offset error in %FS, FS is the full scale
voltage, V_IN is the input voltage being measured, GE is the
gain error in %, ERROR_R is the resistive-divider error in %,
and ERROR_VREF is the voltage reference error in %.
For example, assume:
●● All errors specs are symmetrical.
• |Maximum Positive Error| = |Maximum Negative
Error|
●● The input resistive-divider is made of 1% resistors and
divides the binary voltage by a nominal factor of 240.
• Maximum resistive-divider error ERROR_R = 2%
10
8
6
4
2
0
-2
-4
-6
-8
-10
0.00
0.20
0.40
0.60
0.80
1.00
1.20
V_AIN (V)
UPPER ERROR LIMIT
LOWER ERROR LIMIT
Figure 3. ADC Error Window (Excludes V_REF Error)
●● A nominal 1.25V reference with an error of 5%
• Full-scale input voltage F_S = 1.25V x 240 = 300
• ERROR_VREF = 5%
●● ADC offset error OE = 0.3%
●● ADC gain error GE = 0.3%
●● Input voltage V_IN = 200V
SYSTEM ERROR_MAX = 0.3% x 300V +
V_IN x (0.3%+2%+5% )
When V_IN = 200V, the maximum error is 15.5V.
If the comparator threshold is set at 200V (ADC reading
of decimal 682), the comparator could trip with a voltage
as low as 184.5V or as high as 215.5V. Conversely, if the
ADC is to read 682, the nominal input voltage would be
200V, but the actual voltage could be as high a 215.5V or
as low as 184.5V.
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