DS89C420_02 Datasheet, PDF (49/58 Pages) Maxim Integrated Products – Ultra-High-Speed Microcontroller

DS89C420
NOTES:
1) The system clock frequency is dependent on the oscillator frequency and the setting of the clock-
divide control bits (CD1 and CD0) and the crystal multiplier control bits (4X/ 2X and CTM) in the
PMR register. The term “1 / t_CLCL” used in the variable timing table is calculated through the use of
the table given below.
4X/ 2X
CD1
1
0
0
0
X
0
X
1
X
1
CD0
NUMBER OF OSCILLATOR CYCLE PER
SYSTEM CLOCK (1 / t_CLCL)
0
4 Oscillator Cycles
0
2 Oscillator Cycles
1
Reserved
0
1 Oscillator Cycle
1
1 / 1024 Oscillator Cycle
2) External MOVX instruction times are dependent on the setting of the MD2, MD1, and MD0 bits in
the clock control register. The terms “t_STC1, t_STC2, t_STC3” used in the variable timing table are calculated
through the use of the table given below.
MD2 MD1 MD0
0
00
0
01
0
10
011
100
101
110
111
MOVX
INSTRUCTION
TIME
(MACHINE
CYCLES)
2
3
4
5
9
10
11
12
t_STC1
(t_CLCL)
t_STC2
(t_CLCL)
t_STC3
(t_CLCL)
t_STC4
(t_CLCL)
t_STC5
(t_CLCL)
0
0
0
0
0
2
1
0
0
1
6
1
0
0
1
10
1
0
0
1
14
5
4
1
1
18
5
4
1
1
22
5
4
1
1
26
5
4
1
1
3) Maximum load capacitance (to meet the above timing) for Port 0, ALE, PSEN , WR , and RD is
limited to 60pF. Port 1, 2, 3, and 4 (except for P3.6, WR and P3.7, RD ) are tested with a capacitance
of 50pF. XTAL1 and XTAL2 load capacitance is dependent on the frequency of the selected crystal.
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