DS89C420_02 Datasheet, PDF (40/58 Pages) Maxim Integrated Products – Ultra-High-Speed Microcontroller

DS89C420
EXTERNAL RESET
If the RST input is taken to a logic 1, the device is forced into a reset state. An external reset is
accomplished by holding the RST pin high for at least 3 clock cycles while the oscillator is running. Once
the reset state is invoked, it is maintained as long as RST is pulled to logic 1. When the RST is removed,
the processor exits the reset state within 4 clock cycles and begins execution at address 0000h. If a RST is
applied while the processor is in stop mode, the RST causes the oscillator to begin running and forces the
program counter to 0000h. There is a reset delay of 65,536 clock cycles to allow the oscillator to stabilize.
The RST pin is a bidirectional I/O. If a reset is caused by a power-fail reset, a watchdog timer reset, or an
internal system reset, an output-reset pulse is also generated at the RST pin. This reset pulse is asserted as
long as an internal reset is asserted and may not be able to drive the reset signal out if the RST pin is
connected to an RC circuit. Connecting the RST pin to a capacitor does not affect the internal reset
condition.
OSCILLATOR FAIL DETECT
The DS89C420 incorporates an oscillator fail-detect circuit that, when enabled, causes a reset if the
crystal oscillator frequency falls below 20kHz and holds the chip in reset with the ring oscillator
operating. The circuit is enabled by setting the OFDE (PCON.4) bit to a logic 1. The OFDE bit is only
cleared from a logic 1 to a logic 0 by a power-fail reset or by software. A reset caused by an oscillator
failure also sets the OFDF (PCON.5) to a logic 1. This flag is cleared by software or power-on reset.
Note that this circuit does not force a reset when the oscillator is stopped by the software-enabled stop
mode.
POWER MANAGEMENT MODE
Power management mode offers a software-controllable power-saving scheme by providing a reduced
instruction cycle speed, which allows the DS89C420 to continue to operate while using an internally
divided version of the clock source to save power. Power management mode is invoked by software
setting the clock-divide control bits CD1 and CD0 (PMR.7-6) bits to 11b, which sets an operating rate of
1024 oscillator cycles for 1 machine cycle. On all forms of reset, the clock-divide control bits default to
10b, which selects 1 oscillator cycle per machine cycle.
Since the clock speed choice affects all functional logic including timers, the DS89C420 implements
several hardware switchback features that allow the clock speed to automatically return to the divide-by-1
mode from a reduced cycle rate. This switchback function is enabled by setting the SWB (PMR.5) bit to a
1 in software.
When CD1 and CD0 are programmed to the divide-by-1024 mode and the SWB bit is also enabled, the
system forces the clock-divide control bits to automatically reset to the divide-by-1 mode whenever the
system detects an externally enabled (and allowed through nesting priorities) interrupt. The switchback
occurs whenever one of the two conditions occur. The first switchback condition is initiated by the
detection of a low on either INT 0 , INT1 , INT 3 , or INT 5 , or a high on INT2 or INT4 when the respective
pin has been programmed and allowed (through nesting priorities) to issue an interrupt. The second
switchback condition occurs when either serial port is enabled to receive data and is found to have an
active- low transition on the respective receive input pin. Serial port transmit activity also forces a
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