DS89C420_02 Datasheet, PDF(39/58 Page) Maxim Integrated Products

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DS89C420_02 Datasheet, PDF (39/58 Pages) Maxim Integrated Products – Ultra-High-Speed Microcontroller

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DS89C420

When the DS89C420 enters stop mode, the bandgap, reset comparator, and power- fail interrupt

comparator are automatically disabled to conserve power, if the BGS (EXIF.0) bit is set to a logic 0. This

is the lowest power mode. If BGS is set to a logic 1, the bandgap reference, reset comparator, and the

power- fail comparator are powered up, although in a reduced fashion, while in stop mode.

WATCHDOG TIMER

The watchdog timer functions as the source of both the watchdog interrupt and the watchdog reset. When

the clock divider is set to 10b, the interrupt timeout has a default divide ratio of 217 of the crystal oscillator

clock, with the watchdog reset set to timeout 512 system clock cycles later. This results in a 33MHz

crystal oscillator producing an interrupt timeout every 3.9718ms, followed 15.5Âµs later by a watchdog

reset. The watchdog timer is reset to the default divide ratio following any reset. Using the WD0 and

WD1 bits in the clock control (CKCON.6 and 7) register, other divide ratios can be selected for longer

watchdog interrupt periods. Table 14 summarizes the watchdog bit settings and the timeout values.

Note: All watchdog-timer reset timeouts follow the programmed interrupt timeouts by 512 system clock

cycles, which equates to varying numbers of oscillator cycles depending on the clock-divide (CD1:0) and

crystal multiplier settings.

Table 14. WATCHDOG TIMEOUT VALUE (IN NUMBER OF OSCILLATOR

CLOCKS)

4X/ 2X CD1:0 WATCHDOG INTERRUPT TIMEOUT

WD1:0 = 00 WD1:0 = 01 WD1:0 = 10 WD1:0 = 11

1 00

215

218

221

224

0 00

216

219

222

225

x 01

217

220

223

226

x 10

217

220

223

226

WATCHDOG RESET TIMEOUT

WD1:0 = 00

215 + 128

216 + 256

217 + 512

WD1:0 = 01

218 + 128

219 + 256

220 + 512

WD1:0 = 10

221 + 128

222 + 256

223 + 512

WD1:0 = 11

224 + 128

225 + 256

226 + 512

x 11

227

230

233

236

227 + 524,288 230 + 524,288 233+ 524,288 236 + 524,288

A watchdog control (WDCON) SFR is used for programming the functions. EWT (WDCON.1) is the

enable for the watchdog-timer reset function and RWT (WDCON.0) is the bit used to restart the

watchdog timer. Setting the RWT bit restarts the timer for another full interval. If the watchdog timer

reset function is masked by the EWT bit and no resets are issued to the timer through the RWT bit, the

watchdog timer generates interrupt timeouts at a rate determined by the programmed divide ratio. WDIF

(WDCON.3) is the interrupt flag set at timer termination and WTRF (WDCON.2) is the reset flag set

following a watchdog reset timeout. The watchdog interrupt is enabled by the EWDI bit (EIE.4) when it

is set to 1. The watchdog timer reset and interrupt timeouts are measured by counting system clock

cycles.

An independent watchdog timer functions as the crystal startup counter to count 65,536 crystal clock

cycles before allowing the crystal oscillator to function as the system clock. This warmup time is verified

by the watchdog timer following each power-up as well as each time the crystal is restarted following a

stop mode. The watchdog is also used to establish a startup time whenever the CTM in the PMR register

is set to enable the crystal multiplier (4X/ 2X ).

One of the applications of the watchdog timer is for the watchdog to wake up the system from idle mode.

The watchdog interrupt can be programmed to allow a system to wake up periodically to sample the

external world.

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