DS89C420_02 Datasheet, PDF (31/58 Pages) Maxim Integrated Products – Ultra-High-Speed Microcontroller

Figure 8. PAGE MODE 1, EXTERNAL DATA MEMORY ACCESS
(PAGES = 01, STRETCH = 1, CD = 10)
DS89C420
XTAL1
ALE
PSEN
RD / WR
Port 0
Inst
Inst
MOVX Instruction
MOVX
Inst
Data
Inst
Inst
Port 2
LSB Addr LSB Addr MSB Addr LSB Addr LSB Addr
LSB Addr
Memory Access (Stretch =1)
LSB Addr LSB Addr
ALE
PSEN
RD / WR
MOVX Instruction
Port 0
Inst
MOVX
Inst
Data
Inst
Inst
Inst
Port 2
ALE
PSEN
RD / WR
LSB Addr LSB Addr MSB Addr LSB Addr
LSB Addr
MOVX Inst
Fetch
Memory Access (Stretch =1)
MOVX Instruction
Port 0
Inst
MOVX
Inst
Data
Port 2
LSB Addr LSB Addr LSB Addr MSB Addr
LSB Addr
MOVX Inst
Fetch
Memory Access (Stretch =1)
LSB Addr LSB Addr LSB Addr
Inst
Inst
Inst
LSB Addr LSB Addr LSB Addr
Figure 8 illustrates the external data- memory stretch cycle timing relationship when PAGEE = 1 and
PAGES1:PAGES0 = 01. The stretch cycle shown is for a stretch value of 1 and is coincident with a page
miss. Note that the first stretch value does not result in adding four system clocks to the RD / WR control
signals. This is because the first stretch uses one system clock to create additional setup and one system
clock to create additional hold time.
31 of 58