DS89C420_02 Datasheet, PDF (22/58 Pages) Maxim Integrated Products – Ultra-High-Speed Microcontroller

Figure 3. EXTERNAL PROGRAM MEMORY ACCESS
(NON-PAGE MODE and CD1:CD0 = 10)
Internal Memory Cycles
XTAL1
Ext Memory Cycle
C1 C2 C3 C4
Ext Memory Cycle
C1 C2 C3 C4
ALE
PSEN
Port 0
LSB Add
Data LSB Add
Data
Port 2
MSB Add
MSB Add
DS89C420
EXTERNAL DATA MEMORY INTERFACE IN NON-PAGE MODE OPERATION
Just like the program memory cycle, the external data memory cycle is four times slower than the internal
data memory cycle in non-page mode. A basic internal memory cycle contains one system clock and a
basic external memory cycle contains four system clocks for non-page mode operation.
The DS89C420 allows software to adjust the speed of external data memory access by stretching the
memory bus cycle. CKCON (8Eh) provides an application-selectable stretch value for this purpose.
Software can change the stretch value dynamically by changing the setting of CKCON.2–CKCON.0.
Table 6 shows the data memory cycle stretch values and their effects on the external MOVX- memory bus
cycle and the control signal pulse width in terms of the number of oscillator clocks. A stretch machine
cycle always contains four system clocks.
Table 6. DATA MEMORY CYCLE STRETCH VALUES
MD2:MD0
000
001
010
011
100
101
110
111
STRETCH
CYCLES
0
1
2
3
7
8
9
10
RD / WR PULSE WIDTH (IN NUMBER OF OSCILLATOR CLOCKS)
4X/2X, CD1,
CD0 = 100
4X/2X, CD1,
CD0 = 000
4X/2X, CD1,
CD0 = X10
4X/2X, CD1,
CD0 = X11
0.5
1
2
2048
1
2
4
4096
2
4
8
8192
3
6
12
12288
4
8
16
16384
5
10
20
20480
6
12
24
24576
7
14
28
28672
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