DS8007A Datasheet, PDF (39/41 Pages) Maxim Integrated Products – Multiprotocol Dual Smart Card Interface

Multiprotocol Dual Smart Card Interface
For the T = 0 protocol, only received characters without
parity errors are stored in the receive FIFO. When
UCR1.FIP = 1 during T = 0 reception, only those char-
acters with incorrect parity are stored to the receive
FIFO since the DS8007A is checking for inverse parity.
For the T = 1 protocol, the receive character is stored
to the FIFO no matter whether the parity checks cor-
rectly or not.
If the FIFO threshold enable bits FTE0 and FTE1 are set
to 1, the FIFO implements a programmable threshold
for the assertion of the RBF/TBE bits and the interrupt
line. In this mode, the internal FIFO length is forced to 8
bytes, and FL[2:0] (the programmable FIFO length bits)
determines the threshold value.
Characters are accumulated in the FIFO without setting
the RBF/TBE bits until the FIFO depth is greater than
the threshold value. As long as the used depth is
greater than the FL[2:0] value, the RBF/TBE bits (USR
and MSR) are set and the interrupt pin is asserted.
Reading the FIFO to a level less than or equal to the
threshold value resets the RBF/TBE bit and deasserts
the interrupt line.
Writing a zero or eight into the FL bits while the pro-
grammable threshold mode is enabled causes the
FIFO to behave as it does in nonprogrammable thresh-
old mode.
If the programmable FIFO depth is at its maximum (8
characters) the RBF/TBE bit is set when the eighth
character is received and written into the FIFO. If anoth-
er character is received while the FIFO is full, the over-
flow (OVR) status is set, and the new character
overwrites the previously received character.
If the programmable FIFO depth is set to zero, the
receipt of a single character sets RBF/TBE. Receiving
another character in this state sets the OVR bit and
overwrites the character.
The FIFO empty status bit (FE) operates as before. The
programmable threshold feature functions the same in
T = 0 and T = 1 modes.
Early Answer (EA)
WHEN START BIT
IS ASSERTED
Between 0 and 200 clock
cycles when RSTx = low
Between 200 and 368 clock
cycles when RSTx = low
Between 368 and 400 clock
cycles when RSTx = low
Within the first 368 clock
cycles after RSTx = high
Between 368 and 4000
clock cycles after RSTx =
EA BIT
STATUS
0
1
0
1
0
CHARACTER
RECEIVED
No
Yes
Yes
Yes
Yes
If a start bit is detected on the I/O line during the ATR
between clock cycles 200–368 when the RSTx pin is
low and during the first 368 clock cycles after the RSTx
is high, it is recognized as an early answer (EA), and
the EA bit is set in the USR.EA register. When the EA bit
is set, INT is asserted.
During the early answer detection period, 46 clock
cycles sampling periods should be used to detect the
start bit and there is an undetected (uncertainty) period
of 32 clock cycles at the end for both cases (between
clock cycles 200–368 when the RSTx pin is low, and
the first 368 clock cycles after RSTx is high). Table 6
summarizes the status of the early answer bit. The
answer on the I/O line begins between 400 and 40,000
clock cycles after the rising edge of the RSTx signal.
Development and Technical
Support
The DS8007 evaluation kit (EV kit) is available to assist in
the development of designs using the DS8007/DS8007A
multiprotocol smart card interface. The EV kit can be
purchased directly from Maxim.
For technical support, go to https://support.maxim-
ic.com/micro.
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