DS8007A Datasheet, PDF (24/41 Pages) Maxim Integrated Products – Multiprotocol Dual Smart Card Interface

Multiprotocol Dual Smart Card Interface
UART Status Register (USR)
7
6
5
4
Address 0Eh
TO3
TO2
TO1
EA
R-0
R-0
R-0
R-0
3
2
1
0
PE
OVR
FER
TBE/RBF
R-0
R-0
R-0
R-0
R = unrestricted read, W = unrestricted write, -n = value after reset. All register bits are reset to 00000000b on RIU = 0.
Note: If any of the bits TO3, TO2, TO1, EA, PE, OVR, or FER are set, then a USR read operation clears the bit, causing an interrupt
less than 2µs after the rising edge of the RD strobe. PE and FER can be set by the same reception.
Bits 7 to 5: Timeout Counter 3/2/1 Status (TO3 to
TO1). These bits are set to 1 whenever their respective
timeout counter reaches its terminal count. Any of these
bits causes the INT pin to be asserted.
Bit 4: Early Answer Detected (EA). This bit is set to 1
if a start bit is detected on the I/O line during the ATR
between clock cycles 200–368 when the RSTx pin is
low, and during the first 368 clock cycles after the RSTx
pin is high. When the EA bit becomes set, INT is assert-
ed. If the EA bit is set for a card during ATR, this bit is
cleared when switched to another card. During the
early answer detection period, a 46-clock-cycles sam-
pling period should be used to detect the start bit;
there is an undetected period of 32 clock cycles at the
end for both cases (between clock cycles 200–368
when the RSTx pin is low, and the first 368 clock cycles
after the RSTx pin is high).
Bit 3: Parity Error (PE). This status bit indicates when
the transmit or receive parity error count has been
exceeded. For protocol T = 0, the PEC2–PEC0 bits
define the allowable number of transmit or receive pari-
ty errors. For protocol T = 1, any parity error results in
the setting of the PE bit. When the PE bit is set, INT is
asserted. For protocol T = 0, characters received with
the incorrect parity are not stored in the receive FIFO.
For protocol T = 1, received characters with parity
errors are stored to the receive FIFO regardless of the
parity bit. The PE bit is set at 10.5 ETU in reception
mode and at 11.5 ETU in transmit mode for T = 0 and T
= 1 (PE bit is not applicable for transmit for T = 1).
Bit 2: Overrun FIFO (OVR). This status bit is set to 1 if
the UART receives a new character when the receive
FIFO is full. When a FIFO overrun condition occurs, the
new character received is lost and the previous FIFO
content remains undisturbed. When the OVR status bit
is set, INT is asserted. The OVR bit is set at 10.5 ETU in
receive mode for T = 0 and T = 1.
Bit 1: Framing Error (FER). This status bit is set to 1 if
the I/O line is not in the high state at time = 10.25 ETU
after the start bit. The FER bit is set to 10.5 ETU in
receive mode for T = 0 and T = 1.
Bit 0: Transmit Buffer Empty/Receive Buffer Full
(TBE/RBF). This is a duplicate of the same status bit
contained in the Mixed Status Register (MSR).
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