DS8007A Datasheet, PDF (36/41 Pages) Maxim Integrated Products – Multiprotocol Dual Smart Card Interface

Multiprotocol Dual Smart Card Interface
Block Guard Time
The block guard time for the asynchronous serial com-
munication between the smart card reader (DS8007A)
and the ICC is defined as the minimum delay between
consecutive start bits sent in the opposite direction.
The DS8007A implements an internal ETU counter
specifically to help the host device assess that this min-
imum block guard time is being met. This internal ETU
counter is loaded on each start bit with the value 22d or
16d, dependent upon the protocol selected. For T = 0,
the counter is loaded with the value 16d and for T = 1,
the counter is loaded with the value 22d. If the counter
reaches 0, the MSR.BGT status bit is set and the
counter stops. If a start bit is detected before the
counter reaches 0, the counter is reloaded and the
BGT status bit is cleared to 0.
Transmit Mode
The ISO UART transmit mode is invoked by setting the
associated UCR1.T/R bit to logic 1. When the ISO
UART is placed into transmit mode, the TBE/RBF bit is
set to 1 to indicate that the transmit buffer is empty.
When a character is written to UTR register, the
TBE/RBF bit is cleared to indicate that the transmit
buffer is no longer empty. If the transmit serial shift reg-
ister is available (which is the case unless character
retransmission is occurring), the character is translated
according to the character coding convention (CONV
bit) and moved from the transmit buffer to the serial
shift register. The TBE/RBF bit returns high so that
another character can be loaded into the UTR register.
Guard Time
Some smart cards require extra time to handle informa-
tion received from an interface device. To allow this
extra time, the DS8007A implements a Guard Time
Register (GTR) per card interface. This register is pro-
grammed with the number of extra ETU that should be
enforced between consecutive start bits transmitted by
the DS8007A (discounting retransmissions at the
request of the ICC). The GTR register defaults to 00h
on reset, indicating that no extra guard time is required
(i.e., 12 ETU must be enforced between transmission of
consecutive start bits). If the GTR register is pro-
grammed to FFh, the delay required between consecu-
tive start bits is dependent upon the protocol selected
(per UCR1.PROT).
GTR = FFh
T = 0 protocol: 11.8 ETU
T = 1 protocol: 10.8 ETU
BLOCK GUARD TIME (BGT) COUNTER AND STATUS
BGT COUNTER ≠ 0:
- CLEAR BGT BIT
- RESTART BGT COUNTER
(e.g., 16 ETU FOR T = 0)
BGT COUNTER = 0 (STOPPED):
SET BGT BIT
BGT BIT
I/Ox
Figure 14. Block Guard Time ETU Counter Operation
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