DS8007A Datasheet, PDF (18/41 Pages) Maxim Integrated Products – Multiprotocol Dual Smart Card Interface

Multiprotocol Dual Smart Card Interface
Bit 4: Power-Down Mode Enable (PDWN). This bit
controls entry into the power-down mode. Power-down
mode can only be entered if the SUPL bit has been
cleared. When PDWN is set to 1, the XTAL1 and XTAL2
crystal oscillator is stopped, and basic functions such
as the sequencers are supported by the internal ring
oscillator. The UART is put in a suspended state, and
the clocks to the UART, the ETU unit, and the timeout
counter are gated off. During the power-down mode, it
is not possible to select a card other than the one cur-
rently selected (advisory to the programmer, selecting
another card during power-down mode is not recom-
mended). There are five ways of exiting the power-
down mode:
• Insertion of card A or card B (detected by PRLA or
PRLB).
• Withdrawal of card A or card B (detected by PRLA or
PRLB).
• Reassertion of the CS pin to select the DS8007A (CS
must be deasserted after setting PDWN = 1 for this
event to exit from power-down).
• INTAUXL bit is set due to change in INTAUX
(INTAUXL bit must be cleared first).
• Clearing of PDWN bit by software (if CS pin is always
tied to 0).
Except in the case of a read operation of register HSR,
the INT pin remains asserted in the active-low state.
The host device can read the status registers after the
oscillator warmup time, and the INT signal returns to
the high state.
Bit 3: Synchronous/Asynchronous Card Select
(SAN). This bit selects whether a synchronous or asyn-
chronous card interface is enabled. When this bit is
cleared to 0, an asynchronous card interface is expect-
ed. When this bit is set to 1, a synchronous interface is
expected. In synchronous mode, the UART is
bypassed; the SC bit controls the CLK, and I/O is trans-
acted in the LSb of UTR/URR. Card interface AUX can-
not operate in the true synchronous mode since it does
not have a CLK signal to accompany I/OAUX. However,
the SAN bit invokes the same control of I/OAUX through
UTR/URR as is given for card interfaces A and B.
Bit 2: Auto Convention Disable (AUTOC). This active-
low bit controls whether the decoding convention
should automatically be detected during the first
received character in answer-to-reset (ATR). If AUTOC
= 0, the character decoding convention is automatically
detected (while SS = 1) and the UCR1.CONV bit is writ-
ten accordingly by hardware. If AUTOC = 1, the
UCR1.CONV bit must be set by software to assign the
character decoding convention. The AUTOC bit must
not be changed during a card session.
Bit 1: Clock UART Doubler Enable (CKU). This bit
enables the effective ETU defined for the UART to last
half the number of clock cycles defined by the
AC2–AC0 and PD7–PD0 configuration (except in the
case when AC2–AC0 = 000b, where f_CLK = f_XTAL).
When CKU is cleared to 0, the AC2–AC0 defined f_CLK
is used for ETU timing generation. When CKU is set to
1, a clock frequency of 2 x f_CLK is used for ETU gener-
ation.
Bit 0: Prescaler Select (PSC). When PSC = 0, the
prescaler value is 31. When PSC = 1, the prescaler
value is 32.
Guard Time Register (GTR)
Address 05h
7
GTR.7
RW-0
6
GTR.6
RW-0
5
GTR.5
RW-0
4
GTR.4
RW-0
3
GTR.3
RW-0
2
GTR.2
RW-0
R = unrestricted read, W = unrestricted write, -n = value after reset; all bits unaffected by RIU = 0.
1
GTR.1
RW-0
0
GTR.0
RW-0
Bits 7 to 0: Guard Time Register Bits 7 to 0 (GTR.7
to GTR.0). These bits are used for storing the number
of guard time units (ETU) requested during ATR. When
transmitting, the DS8007A UART delays these numbers
of extra guard time ETU before transmitting a character
written to UTR.
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