DS8007A Datasheet, PDF (38/41 Pages) Maxim Integrated Products – Multiprotocol Dual Smart Card Interface

Multiprotocol Dual Smart Card Interface
Error-Signal Generation
The T=1 protocol does not support error-signal genera-
tion. When configured to receive using the T = 0 proto-
col (UCR1.PROT = 0), the DS8007A supports error-
signal generation in response to parity. The parity error
count bits (PEC2–PEC0) of the FIFO control register
(FCR) determine the number of allowed repetitions in
reception, and therefore the number of times that an
error signal is generated in response to a received
character with incorrect parity before the USR.PE bit
becomes set.
When receiving a character, the DS8007A verifies even
parity for the combination of the received 8-bit charac-
ter and parity bit. If incorrect parity is determined and
consecutive parity error counter has not reached termi-
nal count (000b), the DS8007A generates an error sig-
nal on the I/Ox line starting at 10.5 ETU and lasting for
1.0 ETU. The parity error counter is initialized through
the PEC2–PEC0 bits. Configure the PEC2–PEC0 bits to
000b means that no repetition in reception is allowed
and that an error signal generation occurs in response
to a character received with incorrect parity.
Configuring PEC2–PEC0 bits to 001b means one repe-
tition in reception is allowed and that the DS8007A gen-
erates an error signal only once per character receive
attempt. When the consecutive parity error counter
reaches 000b and a character is received with incor-
rect parity, the USR.PE bit is set to 1. If the parity error
counter has not reached terminal count, it is reset to the
originally programmed value upon reception of a char-
acter having the correct parity. Once the USR.PE bit
signals a parity count error, the software must re-estab-
lish any nonzero PEC2–PEC0 setting.
Receive FIFO
The DS8007A implements an enhanced receive FIFO. If
the FIFO threshold-enable bits FTE0 and FTE1 are set
to 0, the FIFO functions as a standard FIFO that is con-
figurable to a depth of 1 to 8 characters. The T = 0 and
T = 1 protocols allow the FIFO depth to be determined
by the FCR.FL2–FCR.FL0 bits. When configurable, the
FIFO depth is equal to (FL2–FL0) + 1 (e.g., FL2–FL0 =
001b configures the FIFO depth to 2). The RBF/TBE
and FE status bits report the full and empty FIFO condi-
tions, respectively. If the receive FIFO is full (at a maxi-
mum depth of 8), the FIFO Overrun (OVR) bit is set to 1,
the new character received is lost, and the previous
FIFO contents remain undisturbed.
The received characters are read from the URR. When
the receive FIFO is enabled, reads of the URR always
access the oldest available received data. The FIFO is
initialized every time the receive mode is invoked (i.e.,
T/R bit is cleared to 0).
ERROR-SIGNAL GENERATION (T = 0 PROTOCOL ONLY)
IF (INCORRECT PARITY AND PEC ≠ 000b)
HARDWARE ERROR SIGNAL AT 10.5 ETU–11.5 ETU
PARITY BIT DOES NOT CHECK ^{AND DECREMENT PARITY COUNTER.}
IF (CORRECT PARITY AND PE = 0)
RESET PARITY ERROR COUNTER TO
ORIGINAL PEC2–PEC0
PROGRAMMED VALUE.
CHARACTER N
P
CHARACTER N (RETRANSMIT)
P
ETU TIME => 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Figure 16. Receive Mode—Error Signal Generation
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