DS8007A Datasheet, PDF (29/41 Pages) Maxim Integrated Products – Multiprotocol Dual Smart Card Interface

Multiprotocol Dual Smart Card Interface
Deactivation Sequencing
The host device can request a deactivation sequence
by resetting the START bit to 0 for the desired card
interface. The deactivation (from the deassertion of the
START bit, step 1 of the deactivation sequence, to
V_CCx decrease to less than 0.4V) is less than 150µs.
Emergency Deactivation
An emergency deactivation occurs if unsatisfactory
operating conditions are detected. An emergency deac-
tivation occurs for all activated cards in response to a
supply-voltage brownout condition (as reported by the
HSR.SUPL bit) or chip overheating (as reported by
HSR.PTL). Emergency deactivation of an individual card
can occur if a short-circuit condition is detected on the
associated V_CCx or RSTx pin (as reported by
HSR.PRTLx) or in the case of a card takeoff (as reported
by HSR.PRLx). When an emergency deactivation occurs,
hardware automatically forces the associated START
bit(s) to the 0 state. The response of the device to the
emergency deactivation varies according to the source.
If the RSTx pin is shorted or the device overheats, the
sequencer executes a fast emergency deactivation
sequence, which ramps down V_CCX immediately.
If the V_CCX pin was shorted, the sequencer executes a
deactivation sequence in same way as if the START bit
was cleared to 0.
Interrupt Generation
The INT output pin signals the host device that an event
occurred that may require attention. The assertion of
the INT pin is a function of the following sources:
• A fault has been detected on card interfaces
(A or B).
• V_DD has dropped below the acceptable level.
• A reset is caused by externally driving the DELAY
pin to less than 1.25V.
• Excessive heating is detected (i.e., PTL = 1).
• A level change has been detected on pin PRESx or
INTAUX for the card interfaces (A, B, or AUX).
• The parity and/or frame error is detected.
• The early answer (EA) bit is set during ATR.
• The timeout counter(s) reach their terminal
count(s).
• The FIFO full status is reached.
• The FIFO overrun occurs.
• The transmit buffer is empty.
HSR.PRTLA
HSR.PRLA
HSR.PRTLB
HSR.PRLB
HSR.SUPL
HSR.PTL
HSR.INTAUXL
UCR2A.DISAUX
UCR2B.DISAUX
UCR2AUX.DISAUX
USR.TO3
USR.TO2
USR.TO1
USR.EA
USR.PE
USR.OVR
USR.FER
SCA, SCB, SCAUX
USR.TBE/RBF
UCR2A.DISTBE/RBF
UCR2B.DISTBE/RBF
UCR2AUX.DISTBE/RBF
INTERRUPT
GENERATION
INT OUTPUT PIN
SCA, SCB, SCAUX
Figure 10. Interrupt Sources
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