LTC3735 Datasheet, PDF (7/32 Pages) Linear Technology – 2-Phase, High Efficiency DC/DC Controller for Intel Mobile CPUs

TYPICAL PERFORMANCE CHARACTERISTICS
LTC3735
V_RUN/SS Shutdown Latch
Thresholds vs Temperature
4.5
4.0
LATCH ARMING
3.5
3.0
LATCHOFF
THRESHOLD
2.5
2.0
1.5
1.0
0.5
0
–50 –25
0 25 50 75
TEMPERATURE (°C)
100 125
3735 G21
Load Step (Figure 14)
32A
I_OUT
10A/DIV
7.2A
1.364V
V_OUT
100mV/DIV
1.230V
20s/DIV
VID Transition (Figure 14)
1
VIDs
0
1.356V
V_OUT
200mV
/DIV
0.844V
PGOOD
2V/DIV
3735 G22
50s/DIV
3735 G23
PIN FUNCTIONS (G/UHF)
V_FB (Pin 1/Pin 37): Input to the error amplifier that com-
pares the feedback voltage to the internal 0.6V reference
voltage.
DPRSLPVR (Pin 2/Pin 38): Deeper Sleep State Input.
When the signal to this pin is high, the voltage regulator
enters deeper sleep state and its output is determined
by the parallel resistor value of RDPRSLP and RDPSLP.
When the signal is low, the voltage regulator exits deeper
sleep state.
FREQSET (Pin 3/Pin 1): Frequency Set Pin. Apply a DC
voltage between 0V and 5V to set the operating frequency
of the internal oscillator. This frequency is the switching
frequency of each phase.
PSIB (Pin 4/Pin 2): Power Status Indicator Input. When
the signal to this pin is high, both channels operate in fully
synchronous switching mode for fastest transient and
lowest ripple. When the signal is low, controller enters
power saving mode, providing high efficiency at light load.
V_OA+, V_OA– (Pins 5, 6/Pins 3, 4): Inputs to the Internal
Operational Amplifier.
OAOUT (Pin 7/Pin 5): Output of the Internal Operational
Amplifier.
STP_CPUB (Pin 8/Pin 6): Deep Sleep State Input. When the
signal to this pin is low, the voltage regulator enters deep
sleep state and its output voltage is a certain percentage
lower than the VID commands. This offset percentage is
set by the resistor connected to the RDPSLP pin. When
the signal to this pin is high, the voltage regulator exits
deep sleep state.
SGND (Pin 9/Pin 7): Signal Ground. This pin is common
to both controllers. Route separately to the PGND pin.
SENSE1⁺, SENSE2⁺ (Pins 10,12/Pins 8, 9): The (+) Input
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conjunction with R_SENSE set the current trip threshold.
SENSE1^–, SENSE2^– (Pins 11,13/Pins 10, 11): The (–)
Input to Each Differential Current Comparator.
RDPRSLP (Pin 14/Pin 12): Deeper Sleep State Resistor
Pin. Connect a resistor from this pin to V_OA+. This resis-
tor in conjunction with RDPSLP resistor sets the output
voltage of the regulator in deeper sleep state.
RDPSLP (Pin 15/Pin 14): Deep Sleep Resistor Pin. Con-
nect a resistor from this pin to V_OA+. This resistor sets the
percentage offset of output voltage in deep sleep state.
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