LTC3735 Datasheet, PDF (3/32 Pages) Linear Technology – 2-Phase, High Efficiency DC/DC Controller for Intel Mobile CPUs

LTC3735
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T_A = 25°C. V_PVCC = 5V, V_RUN/SS = 5V unless otherwise noted.
SYMBOL PARAMETER
CONDITIONS
Main Control Loop
Reference Regulated Feedback Voltage
I_TH Voltage = 0.5V; Measured at V_FB (Note 4)
V_SENSEMAX Maximum Current Sense Threshold I_TH Voltage = Max; V_CM = 1.7V
l
V_LOADREG Output Voltage Load Regulation
(Note 4)
Measured in Servo Loop, ∆I_TH Voltage: 1.2V to 0.7V l
Measured in Servo Loop, ∆I_TH Voltage: 1.2V to 2V l
V_REFLNREG Reference Voltage Line Regulation V_PVCC = 4.5V to 7V
V_PSIB
Forced Continuous Threshold
I_PSIB
Forced Continuous Current
V_PSIB = 0V
V_OVL
Output Overvoltage Threshold
Measured with Respect to V_FB = 0.6V
g_m
Transconductance Amplifier g_m
I_TH = 1.2V, Sink/Source 25µA (Note 4)
l
g_mOL
Transconductance Amplifier Gain
I_TH = 1.2V, (g_m • Z_L; No Ext Load) (Note 4)
V_ACTIVE
Output Voltage in Active Mode
VID = 010110, I_TH = 0.5V (0°C to 85°C)
VID = 010110, I_TH = 0.5V (Note 2)
l
I_Q
Input DC Supply Current
Normal Mode
Shutdown
(Note 5)
V_RUN/SS = 0V
UVR
Undervoltage RUN/SS Reset
PV_CC Lowered Until the RUN/SS Pin is Pulled Low
I_RUN/SS
Soft-Start Charge Current
V_RUN/SS = 1.9V
VRUN/SS RUN/SS Pin ON Threshold
V_RUN/SS Rising
V_RUN/SSARM RUN/SS Pin Latchoff Arming
V_RUN/SS Rising from 3V
V_RUN/SSLO RUN/SS Pin Latchoff Threshold
V_RUN/SS, Ramping Negative
I_SCL
RUN/SS Discharge Current
Soft-Short Condition V_FB = 0.375V, V_RUN/SS = 4.5V
I_SDLHO
I_SENSE
Shutdown Latch Disable Current
Total Sense Pins Source Current
V_FB = 0.375V, V_RUN/SS = 4.5V
Each Channel: V_{SENSE1–, 2–} = V_{SENSE1+, 2+} = 0V
DF_MAX
Maximum Duty Factor
In Dropout, V_SENSEMAX ≤ 45mV
TG1, 2 t_r
TG1, 2 t_f
Top Gate Transition Time:
Rise Time
Fall Time
(Note 6)
C_LOAD = 3300pF
C_LOAD = 3300pF
BG1, 2 t_r
BG1, 2 t_f
Bottom Gate Transition Time:
Rise Time
Fall Time
(Note 6)
C_LOAD = 3300pF
C_LOAD = 3300pF
TG/BG t_1D Top Gate Off to Bottom Gate On Delay C_LOAD = 3300pF Each Driver (Note 6)
Synchronous Switch-On Delay Time
BG/TG t_2D Bottom Gate Off to Top Gate On Delay C_LOAD = 3300pF Each Driver (Note 6)
Top Switch-On Delay Time
t_ON(MIN)
Minimum On-Time
VID Parameters
Tested with a Square Wave (Note 7)
R_ATTEN
VID Top Resistance
ATTEN_ERR Resistive Divider Error
(Note 8)
l
VID_THLOW VID0 to VID5 Logic Threshold Low
VID_THHIGH VID0 to VID5 Logic Threshold High
VID_LEAK
VID0 to VID5 Leakage
MIN
59
0.57
0.64
4.5
1.342
1.336
3.2
–2.3
1.0
–5
–85
95
–0.25
0.7
TYP
0.600
72
0.1
–0.1
0.02
0.6
–0.5
0.66
6
3
1.356
1.356
2
20
3.7
–1.5
1.5
3.9
3.2
–1.5
1.5
–60
98.5
30
40
60
50
50
60
100
5.33
MAX UNITS
V
85
mV
0.5
–0.5
0.1
0.63
–1
0.68
7.5
1.370
1.376
%
%
%/V
V
µA
V
mmho
V/mV
V
V
3
mA
100
µA
4.2
V
–0.8
µA
1.9
V
V
V
µA
5
µA
µA
%
90
ns
90
ns
90
ns
90
ns
ns
ns
ns
kΩ
0.25
%
0.3
V
V
±1
µA
3735fa
3