LTC3735 Datasheet, PDF (20/32 Pages) Linear Technology – 2-Phase, High Efficiency DC/DC Controller for Intel Mobile CPUs

LTC3735
APPLICATIONS INFORMATION
The masking circuitry also adaptively tracks VID and state
changes. If a new change in VID or state happens before
the 110µs masking timer expires, the timer resets and
starts a fresh count of 110µs. This prevents the system
from rebooting under frequent output voltage transitions.
Refer to Figure 8 for the PGOOD timing diagram.
During start-up, PGOOD is actively pulled low until the RUN/
SS pin voltage reaches its arming voltage, which is 4.2V
typically, only then is the PGOOD pull-low signal released.
When RUN/SS goes low, PGOOD goes low simultaneously.
VID BITS
V_OUT
INTERNAL PG
(OUTPUT OF
INTERNAL
POWER GOOD
COMPARATOR)
PGOOD
MASKING
PGOOD
110µs
110µs
TIME
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Figure 8. PGOOD Timing Diagram
Fault Conditions: Overcurrent Latchoff
The RUN/SS pin also provides the ability to latch off the
controller when an overcurrent condition is detected. The
RUN/SS capacitor, C_SS, is used initially to limit the inrush
current. After the controller has been started and been
given adequate time to charge up the output capacitors
and provide full load current, the RUN/SS capacitor is used
for a short-circuit timer. If the output voltage falls to less
than 70% of its nominal value after C_SS reaches 4.2V, C_SS
begins discharging on the assumption that the output is in
an overcurrent condition. If the condition lasts for a long
enough period as determined by the size of the C_SS, the
controller will be shut down until the RUN/SS pin voltage
is recycled. If the overload occurs during start-up, the
time can be approximated by:
t_LO1 ≈ (C_SS • 0.7V)/(1.5µA) = 4.6 • 10⁵ (C_SS)
If the overload occurs after start-up, the voltage on C_SS
will continue charging and will provide additional time
before latching off:
t_LO2 ≈ (C_SS • 2V)/(1.5µA) = 1.3 • 10⁶ (C_SS)
This built-in overcurrent latchoff can be overridden by
providing a pull-up resistor, R_SS, to the RUN/SS pin as
shown in Figure 6. This resistance shortens the soft-
start period and prevents the discharge of the RUN/SS
capacitor during a severe overcurrent and/or short-circuit
condition. When deriving the 5µA current from PV_CC as in
the figure, current latchoff is always defeated.
Why should you defeat current latchoff? During the pro-
totyping stage of a design, there may be a problem with
noise pickup or poor layout causing the protection circuit
to latch off the controller. Defeating this feature allows
troubleshooting of the circuit and PC layout. The internal
short-circuit and foldback current limiting still remains
active, thereby protecting the power supply system from
failure. A decision can be made after the design is complete
whether to rely solely on foldback current limiting or to
enable the latchoff feature by removing the pull-up resistor.
The value of the soft-start capacitor C_SS may need to be
scaled with output voltage, output capacitance and load
current characteristics. The minimum soft-start capaci-
tance is given by:
C_SS > (C_OUT )(V_OUT)(10^-4)(R_SENSE)
A recommended soft-start capacitor of C_SS = 0.1µF will
be sufficient for most applications.
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