LTC3735 Datasheet, PDF (27/32 Pages) Linear Technology – 2-Phase, High Efficiency DC/DC Controller for Intel Mobile CPUs

LTC3735
APPLICATIONS INFORMATION
SINGLE PHASE
DUAL PHASE
SW V
SW1 V
I_CIN
I_COUT
SW2 V
I_L1
I_L2
I_CIN
I_COUT
RIPPLE
3735 F13
Figure 13. Single and 2-Phase Current Waveforms
The worst-case RMS ripple current for a single stage de-
sign peaks at an input voltage of twice the output voltage.
The worst-case RMS ripple current for a two stage design
results in peak outputs of 1/4 and 3/4 of input voltage.
When the RMS current is calculated, higher effective duty
factor results and the peak current levels are divided as
long as the currents in each stage are balanced. Refer
to Linear Technology Application Note 19 for a detailed
description of how to calculate RMS current for the single
stage switching regulator. Figures 3 and 4 illustrate how
the input and output currents are reduced by using an
additional phase. The input current peaks drop in half and
the frequency is doubled for this 2-phase converter. The
input capacity requirement is thus reduced theoretically
by a factor of four! Ceramic input capacitors with their
low ESR characteristics can be used.
Figure 4 illustrates the RMS input current drawn from
the input capacitance vs the duty cycle as determined
by the ratio of input and output voltage. The peak input
RMS current level of the single phase system is reduced
by 50% in a 2-phase solution due to the current splitting
between the two stages.
An interesting result of the 2-phase solution is that the
V_IN which produces worst-case ripple current for the
input capacitor, V_OUT = V_IN/2, in the single phase design
produces zero input current ripple in the 2-phase design.
The output ripple current is reduced significantly when
compared to the single phase solution using the same
inductance value because the V_OUT/L discharge current
term from the stage that has its bottom MOSFET on sub-
tracts current from the (V_IN – V_OUT)/L charging current
resulting from the stage which has its top MOSFET on.
The output ripple current is:
∆I_RIPPLE
=
2V_OUT
fL



1– 2D (1– D)
1– 2D + 1


where D is duty factor.
The input and output ripple frequency is increased by
the number of stages used, reducing the output capacity
requirements. When V_IN is approximately equal to 2(V_OUT)
as illustrated in Figures 3 and 4, very low input and output
ripple currents result.
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