LTC3735 Datasheet, PDF (14/32 Pages) Linear Technology – 2-Phase, High Efficiency DC/DC Controller for Intel Mobile CPUs

LTC3735
APPLICATIONS INFORMATION
The conduction losses of the top and bottom MOSFETs
are therefore:
( ) P_CONTOP
=
V_OUT
V_IN
•


I_OUT
2


2
•
1+ δ • ∆T
• R_DS(ON)(3)
( ) P_CONBOT
=
V_IN – V_OUT
V_IN
•


I_OUT
2


2
•
1+ δ • ∆T
(4)
• R_DS(ON)
where I_OUT is the total output current at full load, ∆T is the
difference between MOSFET operating temperature and
room temperature, and δ is the temperature dependency
of R_DS(ON). δ is roughly 0.004/°C ~ 0.006/°C for low volt-
age MOSFETs.
The power losses of driving the top and bottom MOSFETs
are simply:
P_DRTOP = Q_G • PV_CC • f
(5)
P_DRBOT = Q_G • PV_CC • f
(6)
Use Q_G data at V_GS = PV_CC in MOSFET data sheets. f is
the switching frequency as described previously. Please
notice that the above gate driving losses are usually not
dissipated by the MOSFETs. Instead they are mainly dis-
sipated on the internal drivers of the LTC3735, if there are
no resistors connected between the drive pins (TG, BG)
and the gates of the MOSFETs.
The calculation of MOSFET switching loss is complicated
by several factors including the wide distribution of power
MOSFET threshold voltage, the nonlinearity of current ris-
ing/falling characteristic and the Miller Effect. Given the
data in a typical power MOSFET data sheet, the switch-
ing losses of the top and bottom MOSFETs can only be
estimated as follows:
P_SWTOP =
per Phase
V_IN2
• I_OUT
4
•
f • C_RSS
• R_DR
•
(7)



V_DR
–
1
V_TH(MIN)
+
1
V_TH(MIN)



P_SWBOT ≈ 0
(8)
where R_DR is the effective driver resistance (of approxi-
mately 2Ω), V_DR is the driving voltage (= PV_CC) and V_TH(MIN)
is the minimum gate threshold voltage of the MOSFET.
Please notice that the switching loss of the bottom MOSFET
is effectively negligible because the current conduction of
the antiparalleling diode. This effect is often referred as
zero-voltage-transition (ZVT). Similarly when the LTC3735
converter works under fully synchronous mode at light
load, the reverse inductor current can also go through
the body diode of the top MOSFET and make the turn-on
loss to be negligible. However, equations 7 and 8 have to
be used in calculating the worst-case power loss, which
happens at highest load level.
The selection criteria of power MOSFETs start with the
stress check:
V_IN < BV_DSS
I_MAX < I_D(MAX)
and
P_CONTOP + P_SWTOP < top MOSFET maximum power
dissipation specification
P_CONBOT + P_SWBOT < bottom MOSFET maximum power
dissipation specification
The maximum power dissipation allowed for each MOSFET
depends heavily on MOSFET manufacturing and pack-
aging, PCB layout and power supply cooling method.
Maximum power dissipation data are usually specified
in MOSFET data sheets under different PCB mounting
conditions.
The next step of selecting power MOSFETs is to minimize
the overall power loss:
P_OVL = P_TOP + P_BOT
= (P_CONTOP + P_DRTOP + P_SWTOP) + (P_CONBOT +
P_DRBOT + P_SWBOT)
For typical mobile CPU applications where the ratio between
input and output voltages is higher than 2:1, the bottom
MOSFET conducts load current most of the time while
the main losses of the top MOSFET are for switching and
driving. Therefore a low R_DS(ON) part (or multiple parts in
parallel) would minimize the conduction loss of the bottom
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