LTC3735 Datasheet, PDF (10/32 Pages) Linear Technology – 2-Phase, High Efficiency DC/DC Controller for Intel Mobile CPUs

LTC3735
OPERATION (Refer to Functional Diagram)
Main Control Loop
The LTC3735 uses a constant frequency, current mode step-
down architecture with the two output stages operating
180 degrees out of phase. During normal operation, each
top MOSFET is turned on when the clock for that channel
sets the RS latch, and turned off when the main current
comparator, I₁, resets the RS latch. The peak inductor
current at which I₁ resets the RS latch is controlled by
the voltage on the I_TH pin, which is the output of error
amplifier EA. The V_OA+ pin receives the voltage feedback
signal, which is compared to the internal reference voltage
by the EA. When the load current increases, it causes a
slight decrease in EA inverting input node relative to the
0.6V reference, which in turn causes the I_TH voltage to
increase until the average inductor current matches the
new load current. After the top MOSFET has turned off,
the bottom MOSFET is turned on until either the inductor
current starts to reverse, as indicated by current compara-
tor I₂, or the beginning of the next cycle.
The top MOSFET drivers are biased from floating bootstrap
capacitor C_B, which normally is recharged during each off
cycle through an external diode when the top MOSFET
turns off. As V_IN decreases to a voltage close to V_OUT,
the loop may enter dropout and attempt to turn on the
top MOSFET continuously. The dropout detector detects
this and forces the top MOSFET off for about 500ns every
sixth cycle to allow C_B to recharge.
The main control loop is shut down by pulling the RUN/
SS pin low. Releasing RUN/SS allows an internal 1.5µA
current source to charge soft-start capacitor C_SS. When
C_SS reaches 1.5V, the main control loop is enabled with
the internal I_TH voltage clamped at approximately 30%
of its maximum value. As C_SS continues to charge, the
internal I_TH voltage is gradually released allowing normal,
full-current operation.
Frequency Programming and Antiphase Operation
The switching frequency of the LTC3735 is determined by
the DC voltage at the FREQSET pin. A DC voltage ranging
from 0V to 2.4V moves the internal oscillator frequency
from 210kHz to 550kHz.
This frequency is the actual switching frequency of either
channel. Because the two channels operate 180°C out of
phase, the apparent frequency at both V_IN and V_OUT is
twice the actual switching frequency, minimizing ripple
voltages and speeding up transient responses.
Low Current Operation (PSIB)
The PSIB pin selects between two modes of operation.
When PSIB is above 0.6V, both channels operate in full
synchronous switching mode. Both bottom drivers (BG1,
BG2) are kept on once they are turned on until their re-
spective oscillator sets the RS latch. The inductor current
can therefore go from output back to input power supply
and could potentially boost the input supply to dangerous
voltage levels—BEWARE! This mode of operation is also
of lower efficiency, given both channels are fully enabled
and much current can circulate between input and output.
However, this mode provides faster transient response,
lower input noise and minimum output ripple.
When PSIB is below 0.6V, the bottom drivers (BG1, BG2)
are turned off if the inductor current starts to reverse. This
mode of operation prevents current going from output
back to input and eliminates the conduction power loss
related to circulating current. If the DPRSLPVR signal
goes high in this mode, Channel 2 will be shut off and
only Channel 1 will be active in supplying load current.
This further eliminates power MOSFET gate driving and
transition losses of Channel 2. Since DPRSLPVR indicates
the entry to deeper sleep state, this “channel shedding”
technique optimizes the voltage regulator efficiency at
light loads. Table 1 summarizes the operation modes for
different pin configurations.
Table 1. Low Current Operation Modes
PSIB DPRSLPVR OPERATION MODE
High High or Low Both Channels ON, Fully Synchronous
Switching, Inductor Current is Allowed to
Reverse
Low
Low Both Channels ON; Reverse Current is
Prevented
Low
High Channel 2 is Shut Off, Reverse Current is
Prevented
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