LTC3838-1_15 Datasheet, PDF (30/52 Pages) Linear Technology – Dual, Fast, Accurate Step-Down DC/DC Controller with Dual Differential Output Sensing

LTC3838-1
APPLICATIONS INFORMATION
Phase and Frequency Synchronization
For applications that require better control of EMI and
switching noise or have special synchronization needs,
the LTC3838-1 can synchronize the turn-on of the top
MOSFET to an external clock signal applied to the MODE/
PLLIN pin. The applied clock signal needs to be within
±30% of the RT programmed frequency to ensure proper
frequency and phase lock. The clock signal levels should
generally comply to V_PLLIN(H) > 2V and V_PLLIN(L) < 0.5V.
The MODE/PLLIN pin has an internal 600k pull-down
resistor to ensure discontinuous current mode operation
if the pin is left open.
The LTC3838-1 uses the voltages on V_IN and V_OUT as well
as R_T to adjust the top gate on-time in order to maintain
phase and frequency lock for wide ranges of V_IN, V_OUT
and R_T-programmed switching frequency f:
t_ON
≈
V_OUT
V_IN • f
As the on-time is a function of the switching regulator’s
output voltage, this output is measured by the SENSE^– pin
to set the required on-time. The SENSE^– pin is tied to the
regulator’s local output point to the IC for most applica-
tions, as the remotely regulated output point could be
significantly different from the local output point due to
line losses, and local output versus local ground is typically
the V_OUT required for the calculation of t_ON.
However, there could be circumstances where this V_OUT
programmed on-time differs significantly different from
the on-time required in order to maintain frequency
and phase lock. For example, lower efficiencies in the
switching regulator can cause the required on-time to be
substantially higher than the internally set on-time (see
Efficiency Considerations). If a regulated V_OUT is relatively
low, proportionally there could be significant error caused
by the difference between the local ground and remote
ground, due to other currents flowing through the shared
ground plane.
If necessary, the R_T resistor value, voltage on the V_IN pin,
or even the common mode voltage of the SENSE pins may
be programmed externally to correct for such systematic
errors. The goal is to set the on-time programmed by V_IN,
V_OUT and R_T close to the steady-state on-time so that the
system will have sufficient range to correct for component
and operating condition variations, or to synchronize to the
external clock. Note that there is an internal 500k resistor
on each SENSE^– pin to SGND, but not on the SENSE⁺ pin.
During dynamic transient conditions either in the line
voltage or load current (e.g., load step or release), the top
switch will turn on more or less frequently in response to
achieve faster transient response. This is the benefit of
the LTC3838-1’s controlled on-time, valley current mode
architecture. However, this process may understandably
lose phase and even frequency lock momentarily. For
relatively slow changes, phase and frequency lock can
still be maintained. For large load current steps with fast
slew rates, phase lock will be lost until the system returns
back to a steady-state condition (see Figure 10). It may
take up to several hundred microseconds to fully resume
the phase lock, but the frequency lock generally recovers
quickly, long before phase lock does.
For light load conditions, the phase and frequency syn-
chronization depends on the MODE/PLLIN pin setting. If
the external clock is applied, synchronization will be active
and switching in continuous mode. If MODE/PLLIN is tied
to INTV_CC, it will operate in forced continuous mode at
the R_T-programmed frequency. If the MODE/PLLIN pin is
tied to SGND, the LTC3838-1 will operate in discontinuous
mode at light load and switch into continuous conduction
at the R_T programmed frequency as load increases. The TG
on-time during discontinuous conduction is intentionally
slightly extended (approximately 1.2 times the continuous
conduction on-time as calculated from V_IN, V_OUT and f) to
create hysteresis at the load-current boundary of continu-
ous/discontinuous conduction.
If an application requires very low (approaching minimum)
on-time, the system may not be able to maintain its full
frequency synchronization range. Getting closer to mini-
mum on-time, it may even lose phase/frequency lock at no
load or light load conditions, under which the SW on-time
is effectively longer than TG on-time due to TG/BG dead
times. This is discussed further under Minimum On-Time,
Minimum Off-Time and Dropout Operation.
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