LTC3838-1_15 Datasheet, PDF (17/52 Pages) Linear Technology – Dual, Fast, Accurate Step-Down DC/DC Controller with Dual Differential Output Sensing

LTC3838-1
OPERATION (Refer to Functional Diagram)
“high” and no greater than 0.5V for “low”. The MODE/
PLLIN pin has an internal 600k pull-down resistor.
Multichip Operations
The PHASMD pin determines the relative phases between
the internal reference clock signals for the two channels
as well as the CLKOUT signal, as shown in Table 2. The
phases tabulated are relative to zero degree (0°) being
defined as the rising edge of the internal reference clock
signal of channel 1. The CLKOUT signal can be used to
synchronize additional power stages in a multiphase power
supply solution feeding either a single high current output,
or separate outputs.
The system can be configured for up to 12-phase opera-
tion with a multichip solution. Typical configurations are
shown in Table 3 to interleave the phases of the channels.
Table 2
PHASMD
Channel 1
Channel 2
CLKOUT
SGND
0°
180°
60°
FLOAT
0°
180°
90°
INTV_CC
0°
240°
120°
Table 3
NUMBER OF
PHASES
2
3
4
6
12
NUMBER OF
LTC3838-1
1
2
2
3
6
PIN CONNECTIONS
[PIN NAME (CHIP NUMBER)]
PHASMD(1) = FLOAT or SGND
PHASMD(1) = INTV_CC
MODE/PLLIN(2) = CLKOUT(1)
PHASMD(1) = FLOAT
PHASMD(2) = FLOAT or SGND
MODE/PLLIN(2) = CLKOUT(1)
PHASMD(1) = SGND
PHASMD(2) = SGND
MODE/PLLIN(2) = CLKOUT(1)
PHASMD(3) = FLOAT or SGND
MODE/PLLIN(3) = CLKOUT(2)
PHASMD(1) = SGND
PHASMD(2) = SGND
MODE/PLLIN(2) = CLKOUT(1)
PHASMD(3) = FLOAT
MODE/PLLIN(3) = CLKOUT(2)
PHASMD(4) = SGND
MODE/PLLIN(4) = CLKOUT(3)
PHASMD(5) = SGND
MODE/PLLIN(5) = CLKOUT(4)
PHASMD(6) = FLOAT or SGND
MODE/PLLIN(6) = CLKOUT(5)
Single-Output PolyPhase Configurations
To use LTC3838-1 for a 2-phase single output step-down
controller: Tie the V_OUTSENSE1+ pin to INTV_CC, which will
disable channel 1’s error amplifier and internally connect
ITH2 to ITH1. Tie the compensation R-C components
to the ITH2 pin. The ITH1 pin can be either left open or
shorted to ITH2 externally. The TRACK/SS1 and PGOOD1
pins become defunct and can be left open. Note that the
RUN1 and RUN2, as well as DTR1 and DTR2 pins still
function for the two channels individually, therefore should
be shorted externally for single-output applications. Set
PHASMD to SGND or FLOAT so that the two channels are
180° out-of-phase. Efficiency losses may be substantially
reduced because the peak current drawn from the input
capacitor is effectively divided by the number of phases
used and power loss is proportional to the RMS current
squared. A 2-phase implementation can reduce the input
path power loss by up to 75%.
To make a single-output converter of three or more phases,
additional LTC3838-1 ICs can be used. The first chip should
be tied the same way as the 2-phase above. If only one
more channel of an additional LTC3838-1 is needed, use
channel 2 for the additional phase:
• Tie the ITH2 pin to the ITH2 pin of the first chip
• Tie the RUN2 pin to the RUN pins of the first chip
• Tie the V_DFB2+ pin to the V_DFB2+ pin of the first chip
• Tie the V_DFB2– pin to the V_DFB2– pin of the first chip
• Tie the TRACK/SS2 pin to the TRACK/SS2 pin of the
first chip
If both channels are needed, the additional LTC3838-1
chip should be tied the same way as the first LTC3838-1
chip to disable the second channel 1’s EA:
• Tie the V_OUTSENSE1+ pin to the chip’s own INTV_CC
• Tie the ITH2 pin to the ITH2 pin of the first chip
• Tie the RUN pins to the RUN pins of the first chip
• Tie the V_DFB2+ pin to the V_DFB2+ pin of the first chip
• Tie the V_DFB2– pin to the V_DFB2– pin of the first chip
• Tie the TRACK/SS2 pin to the TRACK/SS2 pin of the
first chip
38381f
For more information www.linear.com3838-1
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