LTC3838-1_15 Datasheet, PDF (11/52 Pages) Linear Technology – Dual, Fast, Accurate Step-Down DC/DC Controller with Dual Differential Output Sensing

LTC3838-1
PIN FUNCTIONS
V_{OUTSENSE1–} (Pin 13): Differential Output Sense Amplifier
(–) Input of Channel 1. Connect this pin to the negative
terminal of the output load capacitor of V_OUT1.
SENSE1⁺, SENSE2⁺ (Pin 14, Pin 37): Differential Current
Sense Comparator (+) Inputs. The ITH pin voltage and
controlled offsets between the SENSE⁺ and SENSE^– pins
set the current trip threshold. The comparator can be used
for R_SENSE sensing or inductor DCR sensing. For R_SENSE
sensing, Kelvin (4-wire) connect the SENSE⁺ pin to the
(+) terminal of R_SENSE. For DCR sensing, tie the SENSE⁺
pins to the connection between the DCR sense capacitor
and sense resistor tied across the inductor.
SENSE1^–, SENSE2^– (Pin 15, Pin 36): Differential Current
Sense Comparator (–) Input. The comparator can be used
for R_SENSE sensing or inductor DCR sensing. For R_SENSE
sensing, Kelvin (4-wire) connect the SENSE^– pin to the (–)
terminal of R_SENSE. For DCR sensing, tie the SENSE^– pin
to the DCR sense capacitor tied to the inductor V_OUT node
connection. These pins also function as output voltage
sense pins for the top MOSFET on-time adjustment. The
impedance looking into these pins is different from the
SENSE⁺ pins because there is an additional 500k internal
resistor from each of the SENSE^– pins to SGND.
DTR1, DTR2 (Pin 16, Pin 35): Detect Load-Release Tran-
sient for Overshoot Reduction. When load current sud-
denly drops, if voltage on this DTR pin drops below half
of INTV_CC, the bottom gate (BG) could turn off, allowing
the inductor current to drop to zero faster, thus reducing
the V_OUT overshoot. (Refer to Load-Release Transient
Detection in the Applications Information section for more
details.) An internal 2.5μA current source pulls this pin
toward INTV_CC. To disable the DTR feature, simply tie the
DTR pin to INTV_CC.
RUN1, RUN2 (Pin 17, Pin 34): Run Control Inputs. An
internal proportional-to-absolute-temperature (PTAT)
pull-up current source (~1.2µA at 25°C) is constantly
connected to this pin. Taking both RUN1 and RUN2 pins
below a threshold voltage (~0.8V at 25°C) shuts down all
bias of INTV_CC and DRV_CC and places the LTC3838-1 into
micropower shutdown mode. Allowing either RUN pin to
rise above this threshold would turn on the internal bias
supply and the circuitry for the particular channel. When
a RUN pin rises above 1.2V, its corresponding channel’s
TG and BG drivers are turned on and an additional 5µA
temperature-independent pull-up current is connected
internally to the RUN pin. Either RUN pin can sink up to
50µA, or be forced no higher than 6V.
PGOOD1, PGOOD2 (Pin 18, Pin 33): Power Good Indicator
Outputs. This open-drain logic output is pulled to ground
when the output voltage goes out of a ±7.5% window
around the regulation point, after a 50µs power-bad-
masking delay. Returning to the regulation point, there is
a delay of around 20µs to power good, and a hysteresis
of around 2.5% (or 15mV on the same scale as the 0.6V
reference and internal feedback voltages, V_FB1,2) on both
sides of the voltage window.
BOOST1, BOOST2 (Pin 19, Pin 32): Boosted Floating
Supplies for Top MOSFET Drivers. The (+) terminal of the
bootstrap capacitor, C_B, connects to this pin. The BOOST
pins swing by a V_IN between a diode drop below DRV_CC,
or (V_DRVCC – V_D) and (V_IN + V_DRVCC – V_D).
TG1, TG2 (Pin 20, Pin 31): Top Gate Driver Outputs. The
TG pins drive the gates of the top N-channel power MOSFET
with a voltage swing of V_DRVCC between SW and BOOST.
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