LTC3838-1_15 Datasheet, PDF (10/52 Pages) Linear Technology – Dual, Fast, Accurate Step-Down DC/DC Controller with Dual Differential Output Sensing

LTC3838-1
PIN FUNCTIONS
V_DFB2+ (Pin 1): Differential Feedback Amplifier (+) Input
of Channel 2. As shown in the Functional Diagram, con-
nect this pin to a 3-resistor feedback divider network,
which is composed of R_DFB1 and R_DFB2 from this pin to
the negative and positive terminals of V_OUT2 respectively,
and a third resistor from this pin to local SGND. The
third resistor must have a value equal to R_DFB1//R_DFB2
for accurate differential regulation. With the 3-resistor
feedback divider network, the LTC3838‑1 will regulate the
differential output V_OUT2 to 0.6V • (R_DFB1 + R_DFB2)/R_DFB1.
V_RNG (Pin 2): Current Sense Voltage Range Input. The maxi-
mum sense voltage between SENSE1,2⁺ and SENSE1,2^– of
either channel, V_{SENSE(MAX)1,2}, is 30mV if V_RNG is tied to
SGND, and 60mV if V_RNG is tied to INTV_CC.
MODE/PLLIN (Pin 5): Operation Mode Selection or Exter-
nal Clock Synchronization Input. When this pin is tied to
INTV_CC, forced continuous mode operation is selected. Ty-
ing this pin to SGND allows discontinuous mode operation.
When an external clock is applied at this pin, both channels
operate in forced continuous mode and synchronize to the
external clock. This pin has an internal 600k pull-down
resistor to SGND.
CLKOUT (Pin 6): Clock Output of Internal Clock Genera-
tor. Its output level swings between INTV_CC and SGND.
If clock input is present at the MODE/PLLIN pin, it will
be synchronized to the input clock, with phase set by the
PHASMD pin. If no clock is present at MODE/PLLIN, its
frequency will be set by the RT pin. To synchronize other
controllers, it can be connected to their MODE/PLLIN pins.
SGND (Pin 7): Signal Ground. All small-signal analog and
compensation components should be connected to this
ground. Connect SGND to the exposed pad and PGND pin
using a single PCB trace.
RT (Pin 8): Clock Generator Frequency Programming Pin.
Connect an external resistor from RT to SGND to program
the switching frequency between 200kHz and 2MHz. An
external clock applied to MODE/PLLIN should be within
±30% of this programmed frequency to ensure frequency
lock. When the RT pin is floating, the frequency is internally
set to be slightly under 200kHz.
PHASMD (Pin 9): Phase Selector Input. This pin determines
the relative phases of channels and the CLKOUT signal.
With zero phase being defined as the rising edge of TG1:
Pulling this pin to SGND locks TG2 to 180°, and CLKOUT
to 60°. Connecting this pin to INTV_CC locks TG2 to 240°
and CLKOUT to 120°. Floating this pin locks TG2 to 180°
and CLKOUT to 90°.
ITH1, ITH2 (Pin 10, Pin 3): Current Control Threshold. This
pin is the output of the error amplifier and the switching
regulator’s compensation point. The current comparator
threshold increases with this control voltage. The voltage
ranges from 0V to 2.4V, with 0.8V corresponding to zero
sense voltage (zero inductor valley current).
TRACK/SS1, TRACK/SS2 (Pin 11, Pin 4): External Tracking
and Soft-Start Input. The LTC3838-1 regulates differen-
tial feedback voltages (V_OUTSENSE1+ – V_{OUTSENSE1–}) and
(2 • V_DFB2+ – V_DFB2–) to the smaller of 0.6V or the volt-
age on the TRACK/SS1,2 pins respectively. An internal
1µA temperature-independent pull-up current source is
connected to each TRACK/SS pin. A capacitor to ground
at this pin sets the ramp time to the final regulated output
voltage. Alternatively, another voltage supply connected
to this pin allows the output to track the other supply
during start-up.
V_OUTSENSE1+ (Pin 12): Differential Output Sense Amplifier
(+) Input of Channel 1. Connect this pin to a feedback
resistor divider between the positive and negative output
capacitor terminals of V_OUT1 as shown in the Functional
Diagram. In normal operation, the LTC3838-1 will at-
tempt to regulate the differential output voltage V_OUT1
to 0.6V divided by the feedback resistor divider ratio, i.e,
0.6V • (R_FB1 + R_FB2)/R_FB1.
Shorting the V_OUTSENSE1+ pin to INTV_CC will disable
channel 1’s error amplifier, and internally connect ITH1
to ITH2. (As a result, TRACK/SS1 is no longer functional
and PGOOD1 is always pulling low.) By doing so, this
part can function as a dual phase, single V_OUT step-down
controller, and the two channels use a single channel 2
error amplifier for the ITH output and compensation.
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