LTC3838-1_15 Datasheet, PDF (16/52 Pages) Linear Technology – Dual, Fast, Accurate Step-Down DC/DC Controller with Dual Differential Output Sensing

LTC3838-1
OPERATION (Refer to Functional Diagram)
TRACK/SS is pulled low internally when the correspond-
ing channel’s RUN pin is pulled below the 1.2V threshold
(hysteresis applies), or when INTV_CC or either of the
DRV_CC1,2 pins drop below their respective undervoltage
lockout (UVLO) thresholds.
Light Load Current Operation
If the MODE/PLLIN pin is tied to INTV_CC or an external
clock is applied to MODE/PLLIN, the LTC3838-1 will be
forced to operate in continuous mode. With load current
less than one-half of the full load peak-to-peak ripple, the
inductor current valley can drop to zero or become nega-
tive. This allows constant-frequency operation but at the
cost of low efficiency at light loads.
If the MODE/PLLIN pin is left open or connected to signal
ground, the channel will transition into discontinuous mode
operation, where a current reversal comparator (I_REV) shuts
off the bottom MOSFET (M_B) as the inductor current ap-
proaches zero, thus preventing negative inductor current
and improving light-load efficiency. In this mode, both
switches can remain off for extended periods of time. As
the output capacitor discharges by load current and the
output voltage droops lower, EA will eventually move the
ITH voltage above the zero current level (0.8V) to initiate
another switching cycle.
Power Good and Fault Protection
Each PGOOD pin is connected to an internal open-drain
N‑channel MOSFET. An external resistor or current source
can be used to pull this pin up to 6V (e.g., V_OUT1,2 or
DRV_CC). Overvoltage or undervoltage comparators (OV,
UV) turn on the MOSFET and pull the PGOOD pin low
when the feedback voltage is outside the ±7.5% window
of the reference voltage. The PGOOD pin is also pulled low
when the channel’s RUN pin is below the 1.2V threshold
(hysteresis applies), or in undervoltage lockout (UVLO).
When the feedback voltage is within the ±7.5% window,
the open-drain NMOS is turned off and the pin is pulled
up by the external source. The PGOOD pin will indicate
power good immediately after the feedback is within the
window. But when a feedback voltage of a channel goes
out of the window, there is an internal 50µs delay before
its PGOOD is pulled low.
In an overvoltage (OV) condition, M_T is turned off and M_B
is turned on immediately without delay and held on until the
overvoltage condition clears. This happens regardless of
any other condition as long as the RUN pin is enabled. For
example, upon enabling the RUN1 pin, if V_OUT is prebiased
at more than 7.5% above the programmed regulated volt-
age, the OV stays triggered and BG forced on until V_OUT is
pulled a ~2.5% hysteresis below the 7.5% OV threshold.
Foldback current limiting is provided if the output is below
one-half of the regulated voltage, such as being shorted
to ground. As the feedback approaches 0V, the internal
clamp voltage for the ITH pin drops from 2.4V to around
1.3V, which reduces the inductor valley current level to
about 30% of its maximum value. Foldback current limiting
is disabled at start-up.
Frequency Selection and External Clock
Synchronization
An internal oscillator (clock generator) provides phase-
interleaved internal clock signals for individual channels
to lock up to. The switching frequency and phase of each
switching channel is independently controlled by adjust-
ing the top MOSFET turn-on time (on-time) through the
one-shot timer. This is achieved by sensing the phase
relationship between a top MOSFET turn-on signal and
its internal reference clock through a phase detector,
and the time interval of the one-shot timer is adjusted on
a cycle-by-cycle basis, so that the rising edge of the top
MOSFET turn-on is always trying to synchronize to the
internal reference clock signal for the respective channel.
The frequency of the internal oscillator can be programmed
from 200kHz to 2MHz by connecting a resistor, R_T , from
the RT pin to signal ground (SGND). The RT pin is regulated
to 1.2V internally.
For applications with stringent frequency or interference
requirements, an external clock source connected to the
MODE/PLLIN pin can be used to synchronize the internal
clock signals through a clock phase-locked loop (Clock
PLL). The LTC3838-1 operates in forced continuous mode
of operation when it is synchronized to the external clock.
The external clock frequency has to be within ±30% of the
internal oscillator frequency for successful synchroniza-
tion. The clock input levels should be no less than 2V for
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