LTC3863_15 Datasheet, PDF (28/38 Pages) Linear Technology – 60V Low IQ Inverting DC/DC Controller

LTC3863
6. Place the resistive feedback divider R_FB1/2 as close as
possible to the V_FB and V_FBN pins. The (–) terminal
of the feedback divider should connect to the output
regulation point and the (+) terminal of the feedback
divider should connect to V_FB.
7. Place the ceramic C_CAP capacitor as close as possible to
the V_IN and CAP pins. This capacitor provides the gate
discharging current for the power P-channel MOSFET.
8. Place small signal components as close to their respective
pins as possible. This minimizes the possibility of PCB
noise coupling into these pins. Give priority to V_FB, ITH,
and FREQ pins. Use sufficient isolation when routing a
clock signal into the PLLIN /MODE pin so that the clock
does not couple into sensitive small-signal pins.
Failure Mode and Effects Analysis (FMEA)
A FMEA study on the LTC3863 has been conducted through
adjacent pin opens and shorts. The device was tested in
a step-down application (Figure 15) from V_IN = 12V to
V_OUT = –5V with a current load of 2A on the output. One
group of tests involved the application being monitored
while each pin was disconnected from the PC board
and left open while all other pins remained intact. The
other group of tests involved each pin being shorted to
its adjacent pins while all other pins were connected as
it would be normally in the application. The results are
shown in Table 2.
For FMEA compliance, the following design implementa-
tions are recommended:
• If the RUN pin is being pulled up to a voltage greater
than 6V, then it is done so through a pull-up resistor
(100k to 1M) so that the V_FBN pin is not damaged in
case of a RUN to V_FBN short.
• The gate of the external P-channel MOSFET should be
pulled through a resistor (20k to 100k) to the input sup-
ply, V_IN so that the P-channel MOSFET is guaranteed
to turn off in case of a GATE open.
• To protect against the V_FBN open condition it is neces-
sary to add an output shutdown clamp. The output
shutdown clamp is comprised of a Zener, V_Z, NPN and
Zener bias resistor, R_Z, to ground as found in Figure 10.
The clamp voltage will be the Zener forward voltage V_Z
plus a V_BE. The clamp needs to be designed such that
the worst-case minimum Zener voltage is less than
the maximum operating voltage. The worst-case Zener
leakage current times the Zener bias resistor should not
exceed 200mV.
C_Z
R_Z
V_Z
–V_OUT
SS
3863 F10
2N3904
Figure 10
3863fa
28
For more information www.linear.com/3863