LTC3863_15 Datasheet, PDF (26/38 Pages) Linear Technology – 60V Low IQ Inverting DC/DC Controller

LTC3863
Applications Information
An application with complementary dual outputs of ±5V
can be designed by using two LTC3863 parts with one
configured into an inverting regulator and the other into
a step-down buck regulator as shown in Figure 11. Refer
to LTC3864 data sheet for the actual design of a buck
output of 5V.
Gate Driver Component Placement,
Layout and Routing
It is important to follow recommended power supply PC
board layout practices such as placing external power ele-
ments to minimize loop area and inductance in switching
paths. Be careful to pay particular attention to gate driver
component placement, layout and routing.
The effective C_CAP capacitance should be greater than
0.1µF minimum in all operating conditions. Operating
voltage and temperature both decrease the rated capaci-
tance to varying degrees depending on dielectric type. The
LTC3863 is a PMOS controller with an internal gate driver
and boot-strapped LDO that regulates the differential CAP
voltage (V_IN – V_CAP) to 8V nominal. The C_CAP capacitance
needs to be large enough to assure stability and provide
cycle-to-cycle current to the PMOS switch with minimum
series inductance. We recommend a ceramic 0.47µF 16V
capacitor with a high quality dielectric such as X5R or
X7R. Some high current applications with large Qg PMOS
switches may benefit from an even larger C_CAP capacitance.
Figure 8 shows the LTC3863 Generic Application Sche-
matic which includes an optional current sense filter and
series gate resistor. Figure 9 illustrates the recommended
gate driver component placement, layout and routing of
the GATE, V_IN, SENSE and CAP pins and key gate driver
components. It is recommended that the gate driver layout
follow the example shown in Figure 9 to assure proper
operation and long term reliability.
The LTC3863 gate driver should connect to the external
power elements in the following manner. First route the
V_IN pin using a single low impedance isolated trace to
the positive R_SENSE resistor PAD without connection to
the V_IN plane. The reason for this precaution is that the
C_INB
C_SS
C_PITH
C_{ITH RITH}
R_FREQ
GROUND
PLANE
TO PGND
C_CAP
RUN ^CAP V_IN
PLLIN/MODE
SS
SENSE
GATE
LTC3863
ITH
FREQ
SGND
V_FBN
PGND ^VFB
C_SF
R_SF
R_GATE
V_IN
C_IN
+
–^RSENSE
Q1 ^D1
L1
V_OUT
C_OUT
R_FB1
C_FB2 R_FB2
3863 F08
Figure 8: LTC3863 Generic Application Schematic with Optional
Current Sense Filter and Series Gate Resistor
C_INB
GATE
V_IN
SENSE
R_GATE
C_SF
C_CAP
TO Q1 GATE
TO R_SENSE+
CAP
R_SF
TO R_SENSE–
3863 F09
Figure 9: LTC3863 Recommended Gate Driver PC Board
Placement, Layout and Routing
V_IN pin is internally Kelvin connected to the current sense
comparator, internal V_IN power and the PMOS gate driver.
Connecting the V_IN pin to the V_IN power plane adds noise
and can result in jitter or instability. Figure 9 shows a single
V_IN trace from the positive R_SENSE pad connected to C_SF,
C_CAP, V_IN pad and C_INB. The total trace length to R_SENSE
should be minimized and the capacitors C_CF, C_CAP and
C_INB should be placed near the V_IN pin of the LTC3863.
C_CAP should be placed near the V_IN and CAP pins. Figure 9
shows C_CAP placed adjacent to the V_IN and CAP pins with
3863fa
26
For more information www.linear.com/3863