LTC3863_15 Datasheet, PDF (16/38 Pages) Linear Technology – 60V Low IQ Inverting DC/DC Controller

LTC3863
Applications Information
The SENSE pin is a high impedance input with a maximum
leakage of ±2µA. Since the LTC3863 is a peak current
mode controller, noise on the SENSE pin can create pulse
width jitter. Careful attention must be paid to the layout of
R_SENSE. To ensure the integrity of the current sense signal,
V_SENSE, the traces from V_IN and SENSE pins should be
short and run together as a differential pair and Kelvin
(4-wire) connected across R_SENSE (Figure 3).
The LTC3863 has internal filtering of the current sense
voltage which should be adequate in most applications.
However, adding a provision for an external filter offers
added flexibility and noise immunity, should it be neces-
sary. The filter can be created by placing a resistor from the
R_SENSE resistor to the SENSE pin and a capacitor across
the V_IN and SENSE pins.
V_IN
LTC3863
SENSE
OPTIONAL
FILTERING
C_F
R_F
V_IN
R_SENSE
MP
3863 F03
Figure 3. Inductor Current Sensing
Power MOSFET Selection
The LTC3863 drives a P-channel power MOSFET that
serves as the main switch for the nonsynchronous
inverting converter. Important P-channel power MOSFET
parameters include drain-to-source breakdown voltage
BV_DSS, threshold voltage V_GS(TH), on-resistance R_DS(ON),
gate-to-drain reverse transfer capacitance C_RSS, maximum
drain current I_D(MAX), and the MOSFET’s thermal resistance
θ_JC(MOSFET) and θ_JA(MOSFET).
The drain-to-source breakdown voltage must meet the
following condition:
BV_DSS > V_IN(MAX) + |V_OUT| + V_D
The gate driver bias voltage V_IN-V_CAP is set by an internal
LDO regulator. In normal operation, the CAP pin will be
regulated to 8V below V_IN. A minimum 0.1µF capacitor
is required across the V_IN and CAP pins to ensure LDO
stability. If required, additional capacitance can be added
to accommodate higher gate currents without voltage
droop. In shutdown and Burst Mode operation, the CAP
LDO is turned off. In the event of CAP leakage to ground,
the CAP voltage is limited to 9V by a weak internal clamp
from V_IN to CAP. As a result, a minimum 10V V_GS rated
MOSFET is required.
The power dissipated by the P-channel MOSFET when the
LTC3863 is in continuous conduction mode is given by:
P_PMOS
≈D•


I_OUT
1– D


2
•
ρ_T
• R_DS(ON)
( ) ₊ ^{f •C}_MILLER ^{• V}_IN ^{+ | V}_OUT ^{| +V}_D ² _• I_OUT
2
1– D
( ) ^
•_

R_DN
V_IN – V_CAP – V_MILLER
+
R_UP
V_MILLER



where D is duty factor, R_DS(ON) is on-resistance of
P-channel MOSFET, ρ_T is temperature coefficient of on-
resistance, R_DN is the pull-down driver resistance specified
at 0.9Ω typical and R_UP is the pull-up driver resistance
specified at 2Ω typical. V_MILLER is the Miller effective V_GS
voltage and is taken graphically from the power MOSFET
data sheet.
3863fa
16
For more information www.linear.com/3863