LTC3863_15 Datasheet, PDF (27/38 Pages) Linear Technology – 60V Low IQ Inverting DC/DC Controller

LTC3863
Applications Information
SENSE routed between the pads. This is the recommended
layout and results in the minimum parasitic inductance.
The gate driver is capable of providing high peak current.
Parasitic inductance in the gate drive and the series in-
ductance between V_IN to CAP can cause a voltage spike
between V_IN and CAP on each switching cycle. The voltage
spike can result in electrical over-stress to the gate driver
and can result in gate driver failures in extreme cases. It
is recommended to follow the example shown in Figure 9
for the placement of C_CAP as close as is practical.
R_GATE resistor pads can be added with a 0Ω resistor to
allow the damping resistor to be added later. The total
length of the gate drive trace to the PMOS gate should
be minimized and ideally be less than 1cm. In most cases
with a good layout the R_GATE resistor is not needed. The
R_GATE resistor should be located near the gate pin to re-
duce peak current through GATE and minimize reflected
noise on the gate pin.
The R_SF and C_SF pads can be added with a zero ohm resis-
tor for R_SF and C_SF not populated. In most applications,
external filtering is not needed. The current sense filter
R_SF and C_SF can be added later if noise if demonstrated
to be a problem.
The bypass capacitor C_INB is used to locally filter the
V_IN supply. C_INB should be tied to the V_IN pin trace and
to the PGND exposed pad. The C_INB positive pad should
connect to R_SENSE positive though the V_IN pin trace. The
C_INB ground trace should connect to the PGND exposed
pad connection.
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3863.
1. Multilayer boards with dedicated ground layers are
preferable for reduced noise and for heat sinking pur-
poses. Use wide rails and/or entire planes for V_IN, V_OUT
and GND for good filtering and minimal copper loss. If
a ground layer is used, then it should be immediately
below (and/or above) the routing layer for the power
train components which consist of C_IN, sense resistor,
P-channel MOSFET, Schottky diode, inductor, and C_OUT.
Flood unused areas of all layers with copper for better
heat sinking.
2. Keep signal and power grounds separate except at the
point where they are shorted together. Short the signal
and power ground together only at a single point with a
narrow PCB trace (or single via in a multilayer board).
All power train components should be referenced to
power ground and all small-signal components (e.g.,
C_ITH1, R_FREQ, C_SS etc.) should be referenced to the
signal ground.
3. Place C_IN, sense resistor, P-channel MOSFET, induc-
tor, and primary C_OUT capacitors close together in
one compact area. The junction connecting the drain
of the P‑channel MOSFET, cathode of the Schottky,
and (+) terminal of the inductor (this junction is com-
monly referred to as switch or phase node) should be
compact but be large enough to handle the inductor
currents without large copper losses. Place the sense
resistor and source of P-channel MOSFET as close
as possible to the (+) plate of the C_IN capacitor(s)
that provides the bulk of the AC current (these are
normally the ceramic capacitors), and connect the (–)
terminal of the inductor as close as possible to the
(–) terminal of the same C_IN capacitor(s). The high
dI/dt loop formed by C_IN, the MOSFET, and the Schottky
diode should have short leads and PCB trace lengths to
minimize high frequency EMI and voltage stress from
inductive ringing. The (+) terminal of the primary C_OUT
capacitor(s) which filter the bulk of the inductor ripple
current (these are normally the ceramic capacitors)
should also be connected close to the (–) terminal of C_IN.
4. Place Pins 7 to 12 facing the power train components.
Keep high dV/dt signals on GATE and switch away from
sensitive small-signal traces and components.
5. Place the sense resistor close to the (+) terminal of C_IN
and source of P-channel MOSFET. Use a Kelvin (4-wire)
connection across the sense resistor and route the traces
together as a differential pair into the V_IN and SENSE
pins. An optional RC filter could be placed near the V_IN
and SENSE pins to filter the current sense signal.
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