LTC3863_15 Datasheet, PDF (25/38 Pages) Linear Technology – 60V Low IQ Inverting DC/DC Controller

LTC3863
Applications Information
Next choose a P-channel MOSFET with the appropriate
BV_DSS and I_D rating. The BV_DSS rating should be greater
than (55V + 5V + V_D) with sufficient margin. In this ex-
ample, a good choice is the Vishay Si7469DP (BV_DSS =
80V, I_D = 10A, R_DS(ON) = 30mΩ, ρ_100°C = 1.8, V_MILLER =
3.2V, C_MILLER = 235pF, θ_JA = 24°C/W). The highest power
dissipation and the resulting junction temperature for the
P-channel MOSFET occurs at the minimum V_IN of 5V and
maximum output current of 1.8A. They can be calculated
at T_A = 70°C as follows:
D = ^{5V + 0.5V} ≈ 0.55
4.5V + 5V + 0.5V
P_PMOS
=
0.55
•


1.8A
1– 0.55


2
•
1.8
•
30mΩ
+ ^{320kHz • 235pF •(4.5V+| –5V| +0.5V)2}
2
•
1.8A
(1– 0.55)
•


0.9Ω
4.5V – 3.2V
+
2Ω
3.2V


≈ 0.475W + 0.020W ≈ 0.495W
T_J = 70°C + 0.495W • 24°C/W = 82°C
The same calculations can be repeated for V_IN(MAX) = 55V:
D = ^{5V + 0.5V} ≈ 0.091
55V + 5V + 0.5V
P_PMOS
≈
0.091•


1.8A _
1– 0.091^
2
•
1.8
•
30mΩ
+ ^{320kHz • 235pF •(55V+| –5V| +0.5V)2}
2
•
1.8A
(1– 0.091)
•


0.9Ω
5V – 3.2V
+
2Ω
3.2V


≈ 0.019W + 0.39W ≈ 0.411W
T_J = 70°C + 0.411W • 24°C/W = 80°C
Next choose an appropriate Schottky diode that will handle
the power requirements. The reverse voltage of the diode,
V_R, should be greater than (55V + 5V). The Fairchild
S38 Schottky diode is selected (V_F (3A,125°C) = 0.45V,
V_R = 80V, θ_JA = 55°C/W) for this application. The power
dissipation and junction temperature at T_A = 70° and full
load = 1.8A can be calculated as:
P_DIODE = 1.8A • 0.45V = 0.81W
T_J = 70°C + 0.81W • 55°C/W = 114°C
These power dissipation calculations show that careful
attention to heat sinking will be necessary.
For the input bypass capacitors, choose low ESR ceramic
capacitors that can handle the maximum RMS current at
the minimum V_IN of 4.5V:
I_CIN(RMS) ≈ 1.8A •
| –5V|
4.5V
=
1.9A
C_OUT will be selected based on the ESR that is required
to satisfy the output voltage ripple requirement. For this
design, two 47μF ceramic capacitors are chosen to offer
low ripple in both normal operation and in Burst Mode
operation.
The selected C_OUT must support the maximum RMS
operating current at a minimum V_IN of 4.5V:
I_CIN(RMS) ≈ 1.8A •
| –5V| _{= 1.9A}
4.5V
A soft-start time of 8ms can be programmed through a
0.1μF capacitor on the SS pin:
C_SS
=
8ms •10µA
0.8V
=
0.1µF
Loop compensation components on the ITH pin are chosen
based on load step transient behavior (as described under
OPTI-LOOP Compensation) and is optimized for stability. A
pull-up resistor is used on the RUN pin for FMEA compli-
ance (see Failure Modes and Effects Analysis).
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