LTC3863_15 Datasheet, PDF (10/38 Pages) Linear Technology – 60V Low IQ Inverting DC/DC Controller

LTC3863
Operation
LTC3863 Main Control Loop
The LTC3863 is a nonsynchronous inverting PMOS
controller, where an inverting amplifier is used to
sense the negative output voltage below ground. The
LTC3863 uses a peak current mode control architecture
to regulate the output. A feedback resistor, R_FB1, is
placed between V_OUT and V_FBN and a second resistor,
R_FB2, is placed between V_FBN and and V_FB. The LTC3863
has a trimmed internal reference, V_REF, that is equal to
(V_FB – V_FBN). The output voltage is equal to –(R_FB1/R_FB2)
• V_REF where V_REF is equal to 800mV in normal regulation.
The LTC3863 can also be configured as a noninverting
step-down buck regulator when the V_FBN node is pulled
greater than 2V but held less than 5V, which disables the
internal inverting amplifier. A feedback resistor, R_FB1,
is placed between V_OUT and V_FB and a second resistor,
R_FB2, is placed between V_FB and SGND. In the noninvert-
ing buck mode the V_FB input is compared to the internal
reference, V_REF, by a transconductance error amplifier
(EA). The internal reference can be either a fixed 0.8V
reference, V_REF, or the voltage input on the SS pin. In
normal operation V_FB regulates to the internal 0.8V refer-
ence voltage. The output voltage in normal regulation is
equal to (R_FB1 + R_FB2)/R_FB2 • 800mV.
In soft-start or tracking mode when the SS pin voltage
is less than the internal 0.8V reference voltage, V_FB will
regulate to the SS pin voltage. The error amplifier output
connects to the ITH (current [I] threshold [TH]) pin. The
voltage level on the ITH pin is then summed with a slope
compensation ramp to create the peak inductor current
set point.
The peak inductor current is measured through a sense
resistor, R_SENSE, placed across the V_IN and SENSE pins.
The resultant differential voltage from V_IN to SENSE is
proportional to the inductor current and is compared to
the peak inductor current setpoint. During normal opera-
tion the P-channel power MOSFET is turned on when the
clock leading edge sets the SR latch through the S input.
The P-channel MOSFET is turned off through the SR latch
R input when the differential voltage from V_IN to SENSE
is greater than the peak inductor current setpoint and the
current comparator, ICMP, trips high.
Power CAP and V_IN Undervoltage Lockout (UVLO)
Power for the P-channel MOSFET gate driver is derived
from the CAP pin. The CAP pin is regulated to 8V below
V_IN in order to provide efficient P-channel operation. The
power for the V_CAP supply comes from an internal LDO,
which regulates the V_IN-CAP differential voltage. A mini-
mum capacitance of 0.1µF (low ESR ceramic) is required
between V_IN and CAP to assure stability.
For V_IN ≤ 8V, the LDO will be in dropout and the CAP volt-
age will be at ground, i.e., the V_IN-CAP differential voltage
will equal V_IN. If V_IN-CAP is less than 3.25V (typical), the
LTC3863 enters a UVLO state where the GATE is prevented
from switching and most internal circuitry is shut down.
In order to exit UVLO, the V_IN-CAP voltage would have to
exceed 3.5V (typical).
Shutdown and Soft-Start
When the RUN pin is below 0.7V, the controller and most
internal circuits are disabled. In this micropower shutdown
state, the LTC3863 draws only 7µA. Releasing the RUN
pin allows a small internal pull-up current to pull the RUN
pin above 1.26V and enable the controller. The RUN pin
can be pulled up to an external supply of up to 60V or it
can be driven directly by logic levels.
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