LTC3863_15 Datasheet, PDF (22/38 Pages) Linear Technology – 60V Low IQ Inverting DC/DC Controller

LTC3863
Applications Information
3. Gate Charging Loss: Charging and discharging the gate
of the MOSFET will result in an effective gate charg-
ing current. Each time the P-channel MOSFET gate is
switched from low to high and low again, a packet of
charge, dQ, moves from the capacitor across V_IN – V_CAP
and is then replenished from ground by the internal V_CAP
regulator. The resulting dQ/dt current is a current out
of V_IN flowing to ground. The total power loss in the
controller including gate charging loss is determined
by the following equation:
P_CNTRL = V_IN • (I_Q + f • Q_G(PMOSFET))
4. Schottky Loss: The Schottky loss is independent of
duty factors. The critical component is the Schottky
forward voltage as a function of junction temperature
and current. The Schottky power loss is given by the
equation:
P_DIODE = I_OUT • V_D(IOUT,TJ)
When making adjustments to improve efficiency, the input
current is the best indicator of changes in efficiency. If
changes cause the input current to decrease, then the
efficiency has increased. If there is no change in input
current, there is no change in efficiency.
OPTI-LOOP^® Compensation
OPTI-LOOP compensation, through the availability of the
ITH pin, allows the transient response to be optimized for a
wide range of loads and output capacitors. The ITH pin not
only allows optimization of the control loop behavior but
also provides a test point for the regulator ’s DC-coupled
and AC-filtered closed-loop response. The DC step, rise
time and settling at this test point truly reflects the closed-
loop response. Assuming a predominantly second order
system, phase margin and/or damping factor can be
estimated using the percentage of overshoot seen at this
pin. The bandwidth can also be estimated by examining
the rise time at this pin.
The ITH series R_ITH-C_ITH1 filter sets the dominant pole-zero
loop compensation. Additionally, a small capacitor placed
from the ITH pin to signal ground, C_ITH2, may be required to
attenuate high frequency noise. The values can be modified
to optimize transient response once the final PCB layout
is done and the particular output capacitor type and value
have been determined. The output capacitors need to be
selected because their various types and values determine
the loop feedback factor gain and phase. An output current
pulse of 20% to 100% of full load current having a rise
time of 1μs to 10μs will produce output voltage and ITH
pin waveforms that will give a sense of the overall loop
stability without breaking the feedback loop. The general
goal of OPTI-LOOP compensation is to realize a fast but
stable ITH response with minimal output droop due to
the load step. For a detailed explanation of OPTI-LOOP
compensation, refer to Application Note 76.
Switching regulators take several cycles to respond to a
step in load current. When a load step occurs, V_OUT im-
mediately shifts by an amount equal to ∆I_LOAD • ESR, where
ESR is the effective series resistance of C_OUT . ∆I_LOAD also
begins to charge or discharge C_OUT , generating a feedback
error signal used by the regulator to return V_OUT to its
steady-state value. During this recovery time, V_OUT can
be monitored for overshoot or ringing that would indicate
a stability problem.
Connecting a resistive load in series with a power MOSFET,
then placing the two directly across the output capacitor
and driving the gate with an appropriate signal generator
is a practical way to produce a realistic load-step condi-
tion. The initial output voltage step resulting from the step
change in output current may not be within the bandwidth
of the feedback loop, so this signal cannot be used to
determine phase margin. This is why it is better to look
at the ITH pin signal which is in the feedback loop and
is the filtered and compensated feedback loop response.
The gain of the loop increases with R_ITH and the band-
width of the loop increases with decreasing C_ITH1. If R_ITH
is increased by the same factor that C_ITH1 is decreased,
the zero frequency will be kept the same, thereby keeping
the phase the same in the most critical frequency range of
3863fa
22
For more information www.linear.com/3863