LTC3773 Datasheet, PDF (27/32 Pages) Linear Technology – Triple Output Synchronous 3-Phase DC/DC Controller with Up/Down Tracking

LTC3773
APPLICATIONS INFORMATION
nected between the (+) terminal of C_OUT and SGND and
a small decoupling capacitor should be placed across
this divider; as close as possible to the LTC3773 SGND
pin and away from any high current or high frequency
switching nodes.
5. Are the SENSE^– and SENSE⁺ printed circuit traces for
each channel routed together with minimum PC trace
spacing? The filter capacitors between SENSE⁺ and
SENSE^– for each channel should be as close as possible
to the pins of the IC. Connect the SENSE^– and SENSE⁺
pins to the pads of the sense resistor as illustrated in
Figure 9.
6. Keep the switching nodes, SW, BOOST and TG away
from sensitive small-signal nodes (SENSE⁺, SENSE^–,
V_FB, I_TH). Ideally the SW, BOOST and TG printed circuit
traces should be routed away and separated from the IC
and the “quiet” side of the IC. Separate the high dV/dt
printed circuit traces from sensitive small-signal nodes
with ground traces or ground planes.
7. Use a low impedance source such as a logic gate to
drive the PLLIN pin and keep the lead as short as
possible.
8. Minimize trace impedances of TG, BG and SW nets.
TG and SW must be routed in parallel with minimum
distance.
Figure 10 illustrates all branch currents in a three-phase
switching regulator. It becomes very clear after study-
ing the current waveforms why it is critical to keep the
high switching current paths to a small physical size.
High electric and magnetic fields will radiate from these
“loops” just as radio stations transmit signals. The output
capacitor ground should return to the negative terminal
of the input capacitor and not share a common ground
path with any switched current paths. The left half of the
circuit gives rise to the “noise” generated by a switching
regulator. The ground terminations of the synchronous
MOSFETs and Schottky diodes should return to the bot-
tom plate(s) of the input capacitor(s) with a short isolated
PC trace since very high switched currents are present.
A separate isolated path from the bottom plate(s) of the
input and output capacitor(s) should be used to tie in the IC
power ground pin (PGND). This technique keeps inherent
signals generated by high current pulses taking alternate
current paths that have finite impedances during the total
period of the switching regulator. External OPTI-LOOP
compensation allows overcompensation for PC layouts
which are not optimized but this is not the recommended
design procedure.
INDUCTOR
SENSE⁺
LTC3773
SENSE^–
10Ω
1000pF
10Ω
SENSE
RESISTOR
OUTPUT
CAPACITOR
37773 F09
Figure 9. Kelvin Sensing R_SENSE
3773fb
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