LTC3773 Datasheet, PDF (23/32 Pages) Linear Technology – Triple Output Synchronous 3-Phase DC/DC Controller with Up/Down Tracking

LTC3773
APPLICATIONS INFORMATION
MOSFET of controller 1 to be locked to the rising edge of
an external clock signal applied to the PLLIN/FC pin. The
turn-on of controller 2’s/3’s external N-channel MOSFET
and CLKOUT signal are controlled by the PHASEMD
pin as showed in Table 1. Note that when PHASEMD is
forced high, controller 2 and controller 3 outputs can be
connected in parallel to produce a higher output power
voltage source.
Table 1. Phase Relationship between the PLLIN/FC Pin vs
Controller 1, 2, 3 Top Gate and CLKOUT Pin
PHASEMD
GND
Floating
V_CC
CH1
0 Deg
0 Deg
0 Deg
CH2
120 Deg
120 Deg
90 Deg
CH3
240 Deg
240 Deg
270 Deg
CLKOUT
60 Deg
0 Deg
180 Deg
The phase detector is an edge sensitive digital type that
provides zero degrees phase shift between the external
and internal oscillators. This type of phase detector does
not exhibit false lock to harmonics of the external clock.
A simplified Phase-Locked Loop Block Diagram is shown
in Figure 6a. The output of the phase detector is a pair of
complementary current sources that charge or discharge
the external filter network connected to the PLLFLTR pin.
The relationship between the voltage on the PLLFLTR pin
and operating frequency, when there is a clock signal ap-
plied to PLLIN/FC, is shown in Figure 6b and specified in
the Electrical Characteristics table. Note that the LTC3773
can only be synchronized to an external clock whose
frequency is within range of the LTC3773’s internal VCO,
which is nominally 160kHz to 700Hz. This is guaranteed,
over temperature and variations, to be between 200kHz
and 540kHz.
V_CC
R_LP
EXTERNAL
OSCILLATOR
PLLIN/
FC
DIGITAL
PHASE/
FREQUENCY
DETECTOR
C_LP
PLLFLTR
OSCILLATOR
3773 F06a
Figure 6a. Phase-Locked Loop Block Diagram
800
V_CC = 5V
700
600
500
400
300
200
100
0 0.5 1 1.5 2 2.5 3.0
V_PLLFLTR (V)
3773 F06b
Figure 6b. Relationship Between Oscillator Frequency
and Voltage at the PLLFLTR Pin When Synchronizing
to an External Clock
If the external clock frequency is greater than the inter-
nal oscillator’s frequency, f_OSC, then current is sourced
continuously from the phase detector output, pulling up
the PLLFLTR pin. When the external clock frequency is
less than f_OSC, current is sunk continuously, pulling down
the PLLFLTR pin. If the external and internal frequencies
are the same but exhibit a phase difference, the current
sources turn on for an amount of time corresponding to
the phase difference. The voltage on the PLLFLTR pin is
adjusted until the phase and frequency of the oscillators
are identical. At the stable operating point, the phase
detector has high impedance and the filter capacitor C_LP
holds the voltage.
The loop filter components, C_LP and R_LP, smooth out the
current pulses from the phase detector and provide a
stable input to the voltage-controlled oscillator. The filter
components C_LP and R_LP determine how fast the loop ac-
quires lock. Typically R_LP = 10k and C_LP is 0.01μF to 0.1μF.
The external clock (on the PLLIN/FC pin) input threshold
is typically 1V. Table 2 summarizes the different states in
which the PLLIN/FC and PLLFLTR pins can be used.
Table 2. PLLFLTR Pin Voltage vs Switching Frequency
PLLFLTR
GND
Floating
V_CC
RC Loop Filter
PLLIN/FC
DC Voltage
DC Voltage
DC Voltage
Clock Signal
FREQUENCY
220kHz
400kHz
560kHz
Phase-Locked
to External Clock
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