LTC3773 Datasheet, PDF (24/32 Pages) Linear Technology – Triple Output Synchronous 3-Phase DC/DC Controller with Up/Down Tracking

LTC3773
APPLICATIONS INFORMATION
The LTC3773 can be configured to operate at any switch-
ing frequency within the synchronization range. Figure 7
shows a simple circuit to achieve this. The resistive divider
at the PLLFLTR pin programs the LTC3773 switching
frequency according to the transfer curve of Figure 6b. By
connecting the PLLIN/FC pin to the BG1 or the CLKOUT
(UHF package only) node, the pre-set frequency selection
is disengaged and the PLLFLTR pin potential determines
the switching frequency.
PHASE
DETECTOR/
OSCILLATOR
V_CC
OSCILLATOR
V_CC
PLLIN/FC
DIGITAL
PHASE/
FREQUENCY
DETECTOR
BG1
CLKOUT
PLLFLTR
R_PLLFL2
C_LP
R_PLLFL1
3773 F07
Figure 7. Fixed Frequency Adjustment
Minimum On-Time Considerations
Minimum on-time, t_ON(MIN), is the smallest time duration
that the IC is capable of turning on the top MOSFET. It is
determined by internal timing delays and the gate charge
of the top MOSFET. Low duty cycle applications may
approach this minimum on-time limit and care should be
taken to ensure that:
t_ON(MIN)
<
V_OUT
V_IN(f)
If the duty cycle falls below what can be accommodated
by the minimum on-time, the IC will begin to skip every
other cycle, resulting in half-frequency operation. The
output voltage will continue to be regulated, but the ripple
current and ripple voltage will increase.
The minimum on-time for the IC is generally about
130ns. However, as the peak sense voltage decreases,
the minimum on-time gradually increases. This is of par-
ticular concern in forced continuous applications with low
24
ripple current at light loads. If the duty cycle drops below
the minimum on-time limit in this situation, a significant
amount of cycle skipping can occur with correspondingly
larger current and voltage ripple.
If an application can operate close to the minimum on-time
limit, an inductor must be chosen that is low enough in
value to provide sufficient ripple amplitude to meet the
minimum on-time requirement. As a general rule, keep
the inductor ripple current for each channel equal to or
greater than 30% of I_OUT(MAX) at V_IN(MAX).
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can
be expressed as:
%Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percent-
age of input power.
Checking Transient Response
The regulator loop response can be checked by look-
ing at the load transient response. Switching regulators
take several cycles to respond to a step in DC (resistive)
load current. When a load step occurs, V_OUT shifts by an
amount equal to ΔI_LOAD • ESR, where ESR is the effective
series resistance of C_OUT. ΔI_LOAD also begins to charge or
discharge C_OUT, generating the feedback error signal that
forces the regulator to adapt to the current change and
return V_OUT to its steady-state value. During this recovery
time, V_OUT can be monitored for excessive overshoot or
ringing, which would indicate a stability problem. The
availability of the I_TH pin not only allows optimization of
control loop behavior, but also provides a DC coupled and
AC filtered closed-loop response test point. The DC step,
rise time and settling at this test point truly reflects the
closed-loop response. Assuming a predominantly second
order system, phase margin and/or damping factor can be
estimated using the percentage of overshoot seen at this
pin. The bandwidth can also be estimated by examining
the rise time at the pin.
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