LTC3773 Datasheet, PDF (26/32 Pages) Linear Technology – Triple Output Synchronous 3-Phase DC/DC Controller with Up/Down Tracking

LTC3773
APPLICATIONS INFORMATION
that the minimum on-time of 130ns is not violated. The
minimum on-time occurs at maximum V_IN:
t_ON(MIN)
=
V_OUT
V_IN(MAX)f
=
1.8V
22V(220kHz)
=
372ns
The R_SENSE resistor value can be calculated by using the
maximum current sense voltage specification with a con-
servative maximum sense current threshold of 55mV:
R_SENSE

55mV
17.3A

3.2m

Use a commonly available 0.003Ω sense resistor.
Since the output voltage is below 2.4V the output resistive
divider will need to be sized to not only set the output voltage
but also to absorb the SENSE pin’s specified input current.
R1_(MAX)
=
30k^
0.6V
2.4V
V_OUT


=
30k^
0.6V
2.4V
1.8V


=
30k
Choosing 1% resistors; R1 = 10k and R2 = 20k yields an
output voltage of 1.8V.
The power dissipation on the top side MOSFET can be
easily estimated. Choosing a Renesas HAT2168H MOSFET
results in: R_DS(ON) = 13.5mΩ, C_MILLER = 6nC/25V = 240pF.
At maximum input voltage with T (estimated) = 50°C:
P
MAIN⁼
1.8V
 _22V
(15)²
[¹⁺
(0.005)(50°C


25°C)_]
(13.5m)^

+
^(22V)2



15A
2


(2)(240pF)


5
1

1.8
+
1
1.8


(220kHz)^

=
0.612W
Using a Renesas HAT2165H as a bottom MOSFET, the
worst-case power dissipation by the synchronous MOSFET
under normal operating conditions at elevated ambient
temperature and an estimated 50°C junction temperature
rise is:
P_SYNC
=
22V
1.8V
22V
(15)²(1.125)(5.3m)
=
1.23W
26
A short-circuit to ground will result in a folded back
current of
I_SC
=
15mV
0.003


1
2


130ns(22V)
1.5μH 
=
4.05A
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the IC. These items are also illustrated graphically in the
layout diagram of Figure 10. Check the following in the
PC layout:
1. Are the top N-channel MOSFETs located within 1cm of
each other with a common drain connection at C_IN? Do
not attempt to split the input decoupling for the three
channels as it can cause a large resonant loop.
2. Are the signal and power grounds kept separate? Keep
the SGND at one end of a printed circuit path thus
preventing MOSFET currents from traveling under
the IC. The SGND pin should be used to hook up all
control circuitry on one side of the IC. The combined
LTC3773 SGND pin and the ground return of C_VCC must
return to the combined C_OUT (–) terminals. The output
capacitor (–) terminals should be connected as close
as possible to the (–) terminals of the input capacitor
by placing the capacitors next to each other and away
from the charge pump circuitry. The path formed by
the top N-channel MOSFET, Schottky diode and the C_IN
capacitor should have short leads and PC trace lengths.
The power ground returns to the sources of the bottom
N-channel MOSFETs, anodes of the Schottky diodes
and (–) plates of C_IN, which should have as short lead
lengths as possible.
3. The V_CC decoupling capacitor should be placed immedi-
ately adjacent to the IC between the V_CC pin and SGND.
A 1μF ceramic capacitor of the X7R type is small enough
to fit very close to the IC to minimize the ill effects of the
large current pulses drawn to drive the bottom MOSFETs.
An additional 4.7μF to 10μF of ceramic, tantalum or other
very low ESR capacitance is recommended in order to
keep the internal IC supply quiet.
4. Do the LTC3773 V_FB resistive dividers connect to the (+)
terminals of C_OUT? The resistive divider must be con-
3773fb