LTC3773 Datasheet, PDF (13/32 Pages) Linear Technology – Triple Output Synchronous 3-Phase DC/DC Controller with Up/Down Tracking

LTC3773
OPERATION (Refer to the Functional Diagram)
Main Control Loop
The LTC3773 uses a constant frequency, current mode
step down architecture. During normal operation, each
top MOSFET is turned on each cycle when the oscillator
sets the RS latch, and turned off when the main current
comparator, I₁, resets the RS latch. The peak inductor
current at which I₁ resets the RS latch is controlled by
the voltage on the I_TH pin, which is the output of the error
amplifier EA. The error amplifier input pin, V_FB, receives the
output voltage feedback signal from an external resistor
divider. This feedback signal is compared to the internal
0.6V reference voltage by the EA. When the load current
increases it causes a slight decrease in V_FB relative to the
0.6V reference, which in turn causes the I_TH voltage to
increase until the average inductor current matches the
new load current. While the top N-channel MOSFET is off,
the bottom N-channel MOSFET is turned on until either the
next cycle begins or the inductor current starts to reverse,
as indicated by the current reversal comparator, I₂.
The top MOSFET drivers are biased from floating boot-
strap capacitor C_B, which is normally recharged during
each off cycle through an external Schottky diode. When
V_IN decreases to a voltage close to V_OUT, however, the
loop may enter dropout and attempt to turn on the top
MOSFET continuously. The dropout detector counts the
number of oscillator cycles that the bottom MOSFET
remains off and periodically triggers a brief refresh pulse
to recharge C_B.
Shutdown, Soft-Start and Tracking Startup
The main control loop is enabled by allowing the SDBn pin
to go high. In the G package, SDB1, SDB2 and SDB3 are
shorted together at the SDB pin. The power-up thresholds
for channels 1, 2 and 3 are set at 1.2V, 1.8V and 2.4V
respectively. By forcing the SDB1, SDB2 and SDB3 pins
below 0.4V, the IC enters low current shutdown mode, and
the chip draws less than 30μA. Releasing SDBn allows an
internal 0.5μA current source to pull up the SDBn pin. If
a resistive divider connected to V_IN drives the SDB pin,
the controller will automatically start up when V_IN is fully
powered up.
The start-up of V_OUT is controlled by the LTC3773’s TRACK
pin. An external capacitor at the TRACK pin provides the
soft-start function. During soft-start, the error amplifier
EA compares the feedback signal, V_FB, to the TRACK pin’s
potential (instead of the 0.6V reference), which rises linearly
from 0V to 0.6V. This allows the output voltage to rise
smoothly from 0V to its final value while maintaining control
of the inductor current. When the potential at the TRACK
pin approaches the 0.6V reference voltage, the control
loop servos V_FB to the internal reference. The TRACK pin
can also be used for power up/down tracking. A resistor
divider on V_OUT1 connected to the TRACK2/TRACK3 pin
allows the startup of V_OUT2/V_OUT3 to track that of V_OUT1
(refer to the Soft-Start/Tracking section for more detail).
Low Current Operation
The PLLIN/FC pin is a multifunction pin: 1) an external
clock input for PLL synchronization, and 2) a logic input
to select between three modes of operation.
A) Continuous Current Operation: When the PLLIN/FC
pin voltage is above 3V or driven by an external oscil-
lator, the controller performs as a continuous, PWM
current mode synchronous switching regulator. The
top and bottom MOSFETs are alternately turned on to
maintain the output voltage independent of direction
of inductor current. This is the least efficient light load
operating mode, but has lowest output ripple. The
output can source or sink current in this mode. When
sinking current while in forced continuous operation,
the controller can cause current to flow back into the
input supply filter capacitor. Be sure to use an input
capacitor with enough capacitance to prevent the input
voltage from boosting too high. See C_IN and C_OUT Se-
lection in the Applications Information section. Certain
applications must not allow continuous operation at
startup with prebiased output or power down; this can
be easily avoided by shorting the PGOOD output to the
PLLIN/FC pin. The controller will be forced to operate
in Burst Mode until all three outputs are within 10%
of their nominal values.
B) Burst Mode Operation: When the PLLIN/FC pin volt-
age is below 1V and the regulated output voltage is
within 10% of its nominal value, the controller behaves
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