LTC3773 Datasheet, PDF (19/32 Pages) Linear Technology – Triple Output Synchronous 3-Phase DC/DC Controller with Up/Down Tracking

LTC3773
APPLICATIONS INFORMATION
age output current I_MAX equal to the peak value less half
the peak-to-peak ripple current, ΔI_L.
Allowing a margin for variations in the IC and external
component values yields:
R_SENSE
=
55mV
I_MAX
The IC works well with values of R_SENSE from 0.002Ω to
0.1Ω.
Slope Compensation and Inductor Peak Current
Slope compensation provides stability in constant fre-
quency architectures by preventing subharmonic oscilla-
tions at duty cycles greater than 50%. It is accomplished
internally by adding a compensating ramp to the inductor
current signal at duty cycles in excess of 40%. Normally,
at the maximum duty cycle, with slope compensation, the
maximum inductor peak current is reduced by more than
50%, reducing the maximum output current at high duty
cycle operation. However, the LTC3773’s slope compensa-
tion recovery is implemented to allow 70% rated inductor
peak current at the maximum duty cycle.
V_CC and V_DR Power Supplies
Power for the top and bottom MOSFET drivers is derived
from the V_DR pin; the internal controller circuitry is derived
from the V_CC pin. Under typical operating conditions, the
total current consumption at these two pins should be well
below 100mA. Hence, V_DR and V_CC can be connected to an
external auxiliary 5V power supply. If an auxiliary supply is
not available, a simple zener diode and a darlington NPN
buffer can be used to power these two pins as shown in
Figure 3. To prevent switching noise from coupling to the
sensitive analog control circuitry, V_CC should have a 1μF
bypass capacitor, at least, close to the device. The BiCMOS
process that allows the LTC3773 to include large on-chip
MOSFET drivers also limits the maximum V_DR and V_CC
voltage to 7V. This limits the practical maximum auxiliary
supply to a loosely regulated 7V rail. If V_CC drops below
3.9V, LTC3773 goes into undervoltage lockout; if V_DR
drops below V_CC by more than 1V, the driver outputs are
disabled.
R_Z
2k
100Ω
V_Z
6.8V
+
C_IN
Q1
D_B
V_OUT
R_SENSE
+
C_OUT
QT
L
D1
V_IN
C_B
QB
BOOST
TG
SW
BG
LTC3773
Q1: ZETEX FZT603
V_Z: ON SEMI MM5Z6V8ST1
+
10μF
10Ω
+
10μF
0.1μF
0.1μF
V_DR
PGND
V_{CC SGND}
3773 F03
Figure 3. LTC3773 V_CC and V_DR Power Supplies
Topside MOSFET Driver Supply (C_B, D_B)
External bootstrap capacitors, C_B, connected to the
BOOST pins, supply the gate drive voltages for the topside
MOSFETs. Capacitor C_B in Figure 3 is charged though diode
D_B from V_DR when the SW pin is low. When the topside
MOSFETs turns on, the driver places the C_B voltage across
the gate-source of the desired MOSFET. This enhances
the MOSFET and turns on the topside switch. The switch
node voltage, SW, rises to V_IN and the BOOST pin follows.
With the topside MOSFET on, the boost voltage is above
the input supply (V_BOOST = V_DR + V_IN). The value of the
boost capacitor C_B needs to be 30 to 100 times that of the
total gate charge capacitance of the topside MOSFET(s)
as specified on the manufacturer’s data sheet. The reverse
breakdown of D_B must be greater than V_IN(MAX).
Regulator Output Voltage
The regulator output voltages are each set by an external
feedback resistive divider carefully placed across the output
capacitor. The resultant feedback signal is compared with
the internal precision 0.6V voltage reference by the error
amplifier. The output voltage is given by the equation:
V_OUT
=
0.6V



1+
R2 
R1
where R1 and R2 are defined in Figure 1.
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