IS66WVD2M16DALL Datasheet, PDF (50/52 Pages) Integrated Silicon Solution, Inc – Single device supports asynchronous and burst operation

IS66WVD2M16DALL
Figure 35: Asynchronous READ followed by WRITE at the Same Address
Address
ADQ0-
ADQ15
ADV#
CE#
t_AA
VALID
ADDRESS
t_AVS t_AVH
VALID
ADDRESS
t_AADV
t_VP
t_CVP
t_CO
VALID
OUTPUT
t_DS t_DH
VALID
INPUT
UB#/LB#
t_BA
WE#
OE#
t_OLZ
t_OE
HiZ
t_OEW
WAIT
t_WP
t_WZ
HiZ
Notes:
1. The end of the WRITE cycle is controlled by CE#, UB#, LB#, or WE#, whichever de-asserts first.
2. WE# must not remain LOW longer than 4μs (tCEM) while the device is selected (CE# LOW).
Rev. A | May 2012
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