IS66WVD2M16DALL Datasheet, PDF (25/52 Pages) Integrated Silicon Solution, Inc – Single device supports asynchronous and burst operation

IS66WVD2M16DALL
Table 7. Fixed Latency Configuration Codes (BCR[14] = 1)
BCR
[13:11]
010
011
100
101
110
000
others
Latency
Configuration
Code
2 (3 clocks)
3 (4 clocks)-default
4 (5 clocks)
5 (6 clocks)
6 (7 clocks)
8 (9 clocks)
Reserved
Latency
Count (N)
2
3
4
5
6
8
-
Max Input CLK Frequency (MHz)
-75
33 (30ns)
52 (19.2ns)
66 (15ns)
75 (13.3ns)
104 (9.62ns)
133 (7.5ns)
-
-96
33 (30ns)
52 (19.2ns)
66 (15.0ns)
75 (13.3ns)
104 (9.62ns)
-
-
-12
25 (40ns)
40 (25ns)
52 (19.2ns)
66 (15.0ns)
80 (12.5ns)
-
-
Figure 14. Latency Counter (Fixed Latency)
CLK
ADV#
t_AADV
CE#
t_CO
ADQ0-
ADQ15
(READ)
ADQ0-
ADQ15
(WRITE)
t_AA
VALID
ADDRESS
VALID
ADDRESS
Burst Identified
(ADV#=LOW)
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
INPUT
VALID
INPUT
VALID
INPUT
Operating Mode (BCR[15]) Default = Synchronous Operation
The operating mode bit enables synchronous burst operation or limits the device to the
asynchronous mode of operation only. If the clock is stopped LOW, all accesses are
asynchronous, even when synchronous mode is enabled.
Rev. A | May 2012
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