IS66WVD2M16DALL Datasheet, PDF (27/52 Pages) Integrated Silicon Solution, Inc – Single device supports asynchronous and burst operation

IS66WVD2M16DALL
Partial-Array Refresh (RCR[2:0]) Default = Full Array Refresh
The PAR bits restrict refresh operation to a portion of the total memory array. This
feature allows the device to reduce standby current by refreshing only that part of the
memory array required by the host system. The refresh options are full array, one-half
array, one-quarter array, one-eighth array, or none of the array. The mapping of these
partitions can start at either the beginning or the end of the address map (see Tables 9)
Table 9. 32Mb Address Patterns for PAR (RCR[4]=1)
RCR[2] RCR[1]
RCR[0]
Active Section
0
0
0
Full
0
0
1
Bottom 1/2 array
0
1
0
Bottom 1/4 array
0
1
1
Bottom 1/8 array
1
0
0
None of array
1
0
1
Top 1/2 array
1
1
0
Top 1/4 array
1
1
1
Top 1/8 array
Address Space
000000h ~ 1FFFFFh
000000h ~ 0FFFFFh
000000h ~ 07FFFFh
000000h ~ 03FFFFh
0
100000h ~ 1FFFFFh
180000h ~ 1FFFFFh
1C0000h ~ 1FFFFFh
Size
2MX16
1MX16
512KX16
256KX16
1MX16
512KX16
256KX16
Density
32Mb
16Mb
8Mb
4Mb
0Mb
16Mb
8Mb
4Mb
Deep Power-Down (RCR[4]) Default = DPD Disabled
The deep power-down bit enables and disables all refresh-related activity. This mode is
used if the system does not require the storage provided by the CellularRAM device. Any
stored data will become corrupted when DPD is enabled. When refresh activity has been
re-enabled, the CellularRAM device will require 150μs to perform an initialization
procedure before normal operations can resume.
Deep power-down is enabled by setting RCR[4] = 0 and taking CE# HIGH. Taking CE# LOW
disables DPD and sets RCR[4] = 1; it is not necessary to write to the RCR to disable DPD. DPD
can be enabled using CRE or the software sequence to access the RCR. BCR and RCR
values (other than BCR[4]) are preserved during DPD.
Device Identification Register
The DIDR provides information on the device manufacturer, CellularRAM generation,
and the specific device configuration. Table 10 describes the bit fields in the DIDR. This
register is read-only.
The DIDR is accessed with CRE HIGH and A[19:18] = 01b, or through the software access
sequence with ADQ = 0002h on the third cycle.
Table 10. Device Identification Register Mapping
Bit Field
DIDR[15]
DIDR[14:11]
DIDR[10:8]
Field Name
Row Length
Device Version
Device Density
Length
- words
128
256
Bit
Setting
0b
1b
Version
1st
2nd
Bit
Setting
0000b
0001b
Density
16Mb
32Mb
Bit
Setting
000b
001b
DIDR[7:5]
CellularRAM
Generation
Genera
Bit
tion _Setting
CR1.5 010b
CR2.0 011b
DIDR[4:0]
Vendor ID
Vendor
ISSI
Bit
Setting
00101b
Rev. A | May 2012
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